SLVSHB1A March   2023  – November 2024 DRV8329-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 2pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three BLDC Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 6x PWM Mode
          2. 7.3.1.1.2 3x PWM Mode
        2. 7.3.1.2 Device Hardware Interface
        3. 7.3.1.3 Gate Drive Architecture
          1. 7.3.1.3.1 Propagation Delay
          2. 7.3.1.3.2 Deadtime and Cross-Conduction Prevention
      2. 7.3.2 AVDD Linear Voltage Regulator
      3. 7.3.3 Pin Diagrams
      4. 7.3.4 Low-Side Current Sense Amplifiers
        1. 7.3.4.1 Current Sense Operation
      5. 7.3.5 Gate Driver Shutdown Sequence (DRVOFF)
      6. 7.3.6 Gate Driver Protective Circuits
        1. 7.3.6.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.6.2 AVDD Power on Reset (AVDD_POR)
        3. 7.3.6.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.6.4 BST Undervoltage Lockout (BST_UV)
        5. 7.3.6.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.6.6 VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.6.7 Thermal Shutdown (OTSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gate Driver Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (nSLEEP Reset Pulse)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Three Phase Brushless-DC Motor Control
        1. 8.2.1.1 Detailed Design Procedure
          1. 8.2.1.1.1  Motor Voltage
          2. 8.2.1.1.2  Bootstrap Capacitor and GVDD Capacitor Selection
          3. 8.2.1.1.3  Gate Drive Current
          4. 8.2.1.1.4  Gate Resistor Selection
          5. 8.2.1.1.5  System Considerations in High Power Designs
            1. 8.2.1.1.5.1 Capacitor Voltage Ratings
            2. 8.2.1.1.5.2 External Power Stage Components
            3. 8.2.1.1.5.3 Parallel MOSFET Configuration
          6. 8.2.1.1.6  Dead Time Resistor Selection
          7. 8.2.1.1.7  VDSLVL Selection
          8. 8.2.1.1.8  AVDD Power Losses
          9. 8.2.1.1.9  Current Sensing and Output Filtering
          10. 8.2.1.1.10 Power Dissipation and Junction Temperature Losses
      2. 8.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance Sizing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Thermal Considerations
        1. 8.4.2.1 Power Dissipation
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Related Links
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Community Resources
    6. 9.6 Trademarks
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DRV8329-Q1 DRV8329 RGF Package40-pin VQFN With Exposed Thermal PadTop View Figure 5-1 DRV8329 RGF Package40-pin VQFN With Exposed Thermal PadTop View
Table 5-1 Pin Functions—40-Pin DRV8329-Q1 Devices
NAME PIN NO. TYPE(1) DESCRIPTION
DRV8329
NC 1 — No connection.
NC 2 — No connection.
NC 3 — No connection.
GND 4 PWR Device ground. Refer Section 8.4.1 for the recommendation on connection.
PVDD 5 PWR Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1µF, >2x PVDD-rated ceramic and >10uF local capacitance between the PVDD and GND pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.
NC 6 — No connection.
CPL 7 PWR Charge pump switching node. Connect a X5R or X7R, PVDD-rated ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.
CPH 8 PWR
GVDD 9 PWR-O Gate driver power supply output. Connect a X5R or X7R, 30V rated ceramic ≥ 10-uF local capacitance between the GVDD and GND pins. TI recommends a capacitor value of >10x CBSTx and voltage rating at least twice the normal operating voltage of the pin.
BSTA 10 O Bootstrap output pin. Connect a X5R or X7R, 1µF, 25V ceramic capacitor between BSTA and SHA
SHA 11 I/O High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
GHA 12 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 13 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
BSTB 14 O Bootstrap output pin. Connect a X5R or X7R, 1µF, 25V ceramic capacitor between BSTB and SHB
SHB 15 I/O High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
GHB 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLB 17 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
BSTC 18 O Bootstrap output pin. Connect a X5R or X7R, 1µF, 25V ceramic capacitor between BSTC and SHC
SHC 19 I/O High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
GHC 20 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLC 21 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
LSS 22 PWR Low side source pin, connect all sources of the external low-side MOSFETs here. This pin is the sink path for the low-side gate driver, and serves as an input to monitor the low-side MOSFET VDS voltage and VSEN_OCP voltage.
SP 23 I Current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SN 24 I Current sense amplifier input. Connect to the low-side of the current shunt resistor.
DRVOFF 25 I Independent driver shutdown path. Pulling DRVOFF high turns off all external MOSFETs by putting the gate drivers into the pull-down state. This signal bypasses and overrides the digital core of DRV8329.
AGND 26 PWR Device analog ground. Refer Section 8.4.1 for the recommendation on connection.
AVDD 27 PWR-O 3.3V regulator output. Connect a X5R or X7R, 1µF, >6.3V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 80mA externally. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.
INHC 28 I High-side gate driver control input for Phase C. This pin controls the output of the high-side FET (DRV8329A) or controls the output of the half-bridge (DRV8329B).
INHB 29 I High-side gate driver control input for Phase B. This pin controls the output of the high-side FET (DRV8329A) or controls the output of the half-bridge (DRV8329B).
INHA 30 I High-side gate driver control input for Phase A. This pin controls the output of the high-side FET (DRV8329A) or controls the output of the half-bridge (DRV8329B).
INLC 31 I Low-side gate driver control input for Phase C. This pin controls the output of the low-side FET (DRV8329A) or controls high-Z mode for the half bridge (DRV8329B).
INLB 32 I Low-side gate driver control input for Phase B. This pin controls the output of the low-side FET (DRV8329A) or controls high-Z mode for the half bridge (DRV8329B).
INLA 33 I Low-side gate driver control input for Phase A. This pin controls the output of the low-side FET (DRV8329A) or controls high-Z mode for the half bridge (DRV8329B).
CSAGAIN 34 I Gain settings for Current sense amplifier. The pin is a 4 level input pin set by an external resistor. See Section 7.3.4 for more information.
nSLEEP 35 I Sleep mode entry pin. When this pin is pulled logic low the device goes to a low-power sleep mode. An 1 to 1.2µs low pulse can be used to reset fault conditions without entering sleep mode.
nFAULT 36 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor to 3.3V to 5.0V.
VDSLVL 37 I VDS monitor trip point setting. Connect an analog level input from 0.1V to 2.5V to set a VDS monitor trip point setting for MOSFET overcurrent protection. See Section 8.2.1.1.7 for more information.
CSAREF 38 I Current sense amplifier reference. Connect a X5R or X7R, 0.1µF, 6.3V ceramic capacitor between the CSAREF and AGND pins.
SO 39 O Current sense amplifier output. Supports capacitive load or low pass filter (resistor in series and capacitor to AGND)
DT 40 I Gate drive deadtime setting. Connect a resistor of value between 10kΩ to 390kΩ between DT and AGND to adjust deadtime between 100ns to 2000ns. If pin is left floating or connected to AGND fixed value of 55ns deadtime is inserted.
Thermal Pad PWR Must be connected to GND
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain output