SLVSHB1A March   2023  – November 2024 DRV8329-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 2pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three BLDC Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 6x PWM Mode
          2. 7.3.1.1.2 3x PWM Mode
        2. 7.3.1.2 Device Hardware Interface
        3. 7.3.1.3 Gate Drive Architecture
          1. 7.3.1.3.1 Propagation Delay
          2. 7.3.1.3.2 Deadtime and Cross-Conduction Prevention
      2. 7.3.2 AVDD Linear Voltage Regulator
      3. 7.3.3 Pin Diagrams
      4. 7.3.4 Low-Side Current Sense Amplifiers
        1. 7.3.4.1 Current Sense Operation
      5. 7.3.5 Gate Driver Shutdown Sequence (DRVOFF)
      6. 7.3.6 Gate Driver Protective Circuits
        1. 7.3.6.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.6.2 AVDD Power on Reset (AVDD_POR)
        3. 7.3.6.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.6.4 BST Undervoltage Lockout (BST_UV)
        5. 7.3.6.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.6.6 VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.6.7 Thermal Shutdown (OTSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gate Driver Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (nSLEEP Reset Pulse)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Three Phase Brushless-DC Motor Control
        1. 8.2.1.1 Detailed Design Procedure
          1. 8.2.1.1.1  Motor Voltage
          2. 8.2.1.1.2  Bootstrap Capacitor and GVDD Capacitor Selection
          3. 8.2.1.1.3  Gate Drive Current
          4. 8.2.1.1.4  Gate Resistor Selection
          5. 8.2.1.1.5  System Considerations in High Power Designs
            1. 8.2.1.1.5.1 Capacitor Voltage Ratings
            2. 8.2.1.1.5.2 External Power Stage Components
            3. 8.2.1.1.5.3 Parallel MOSFET Configuration
          6. 8.2.1.1.6  Dead Time Resistor Selection
          7. 8.2.1.1.7  VDSLVL Selection
          8. 8.2.1.1.8  AVDD Power Losses
          9. 8.2.1.1.9  Current Sensing and Output Filtering
          10. 8.2.1.1.10 Power Dissipation and Junction Temperature Losses
      2. 8.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance Sizing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Thermal Considerations
        1. 8.4.2.1 Power Dissipation
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Related Links
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Community Resources
    6. 9.6 Trademarks
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 ESD Ratings Auto

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2		 ±2000 V
Charged device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B		 Corner pins ±750
Other pins ±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.