The DRV8340-Q1 device is an integrated gate driver for three-phase applications. The device provides three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The dedicated Source and Drain pins enable the independent MOSFET control for solenoid application. The DRV8340-Q1 generates the correct gate drive voltages using an integrated charge pump sufficient for the high-side MOSFETs and a linear regulator for the low-side MOSFETs. The Smart Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A. The DRV8340-Q1 can operate from a single power supply and supports a wide input supply range of 5.5 to 60 V for the gate driver.
The 6x, 3x, 1x, and independent input PWM modes allow for simple interfacing to controller circuits. The configuration settings for the gate driver and device are highly configurable through the SPI or hardware (H/W) interface.
A low-power sleep mode is provided to achieve low quiescent current. Internal protection functions are provided for undervoltage lockout, charge pump fault, MOSFET overcurrent, MOSFET short circuit, phase-node short to supply and ground, gate driver fault, and overtemperature. Fault conditions are indicated on the nFAULT pin with details through the device registers for the SPI device variant.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8340-Q1 | HTQFP (48) | 7.00 mm × 7.00 mm |
DATE | REVISION | NOTES |
---|---|---|
May 2019 | * | Initial Release |
DEVICE | VARIANT(1) | INTERFACE(1) |
---|---|---|
DRV8340-Q1 | DRV8340H | Hardware |
DRV8340S | SPI |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | CPL | PWR | Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins |
2 | CPH | PWR | Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins |
3 | VCP | PWR | Charge pump output. Connect a bypass capacitor between the VCP and VM pins |
4 | VM | PWR | Gate driver power supply input. Connect to the bridge power supply. Connect bypass capacitors VM and PGND pins |
5 | VDRAIN | I | High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains |
6 | GHA | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET |
7 | SHA | I | High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used, connect to GND |
8 | DLA | I | Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain |
9 | GLA | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET |
10 | SLA | I | Low-side source sense input. Connect to the low-side power MOSFET source |
11 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
12 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
13 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
14 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
15 | SLB | I | Low-side source sense input. Connect to the low-side power MOSFET source |
16 | GLB | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET |
17 | DLB | I | Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain |
18 | SHB | I | High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used, connect to GND |
19 | GHB | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET |
20 | GHC | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET |
21 | SHC | I | High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used, connect to GND |
22 | DLC | I | Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain |
23 | GLC | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET |
24 | SLC | I | Low-side source sense input. Connect to the low-side power MOSFET source |
25 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
26 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
27 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
28 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
29 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
30 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
31 | nFAULT | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor |
32 | MODE | I | PWM input mode setting. This pin is a 7-level input pin set by an external resistor |
33 | IDRIVE | I | Gate drive output current setting. This pin is a 7-level input pin set by an external resistor |
34 | VDS | I | VDS monitor trip point setting. This pin is a 7-level input pin set by an external resistor |
35 | RSVD | I | Reserved. Leave open. |
36 | ENABLE | I | Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 20-μs (typ) low pulse can be used to reset fault conditions |
37 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
38 | AGND | PWR | Device analog ground. Connect to system ground |
39 | DVDD | PWR | 3.3-V internal regulator output. Connect a bypass capacitor between the DVDD and AGND pins. This regulator can externally source up to 30 mA. |
40 | nDIAG | I | Control pin for open load diagnostic and offline short-to-battery and short-to-ground diagnostic. To enable the diagnostics at device power-up, do not connect this pin (or tie it to ground). To disable the diagnostics, connect this pin to the DVDD pin. |
41 | INHA | I | High-side gate driver control input. This pin controls the output of the high-side gate driver |
42 | INLA | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver |
43 | INHB | I | High-side gate driver control input. This pin controls the output of the high-side gate driver |
44 | INLB | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver |
45 | INHC | I | High-side gate driver control input. This pin controls the output of the high-side gate driver |
46 | INLC | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver |
47 | PGND | PWR | Device power ground. Connect to system ground |
48 | NC | NC | No connect. Do not connect anything to this pin |
— | Thermal Pad | PWR | Must be connected to ground |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | CPL | PWR | Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins |
2 | CPH | PWR | Charge pump switching node. Connect a flying capacitor between the CPH and CPL pins |
3 | VCP | PWR | Charge pump output. Connect a bypass capacitor between the VCP and VM pins |
4 | VM | PWR | Gate driver power supply input. Connect to the bridge power supply. Connect bypass capacitors between the VM and PGND pins |
5 | VDRAIN | I | High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains |
6 | GHA | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET |
7 | SHA | I | High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used, connect to GND |
8 | DLA | I | Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain |
9 | GLA | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET |
10 | SLA | I | Low-side source sense input. Connect to the low-side power MOSFET source |
11 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
12 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
13 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
14 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
15 | SLB | I | Low-side source sense input. Connect to the low-side power MOSFET source |
16 | GLB | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET |
17 | DLB | I | Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain |
18 | SHB | I | High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used, connect to GND |
19 | GHB | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET |
20 | GHC | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET |
21 | SHC | I | High-side source sense input. Connect to the high-side power MOSFET source. If high-side power MOSFET is not used, connect to GND |
22 | DLC | I | Low-side MOSFET drain sense input. Connect to the low-side MOSFET drain |
23 | GLC | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET |
24 | SLC | I | Low-side source sense input. Connect to the low-side power MOSFET source |
25 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
26 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
27 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
28 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
29 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
30 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
31 | nFAULT | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor |
32 | SDO | PP | Serial data output. Data is shifted out on the rising edge of the SCLK pin. VSDO determines logic level on the output |
33 | SDI | I | Serial data input. Data is captured on the falling edge of the SCLK pin |
34 | SCLK | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin |
35 | nSCS | I | Serial chip select. A logic low on this pin enables serial interface communication |
36 | ENABLE | I | Gate driver enable. When this pin is logic low the device goes to a low-power sleep mode. An 20-μs (typ) low pulse can be used to reset fault conditions |
37 | NC | NC | No internal connection. This pin can be left floating or connected to system ground. |
38 | AGND | PWR | Device analog ground. Connect to system ground |
39 | DVDD | PWR | 3.3-V internal regulator output. Connect a bypass capacitor between the DVDD and AGND pins. This regulator can externally source up to 30 mA. |
40 | VSDO | PWR | Supply pin for SDO output. Connect to 5-V or 3.3-V depending on the desired logic level. Connect a bypass capacitors between VSDO and AGND |
41 | INHA | I | High-side gate driver control input. This pin controls the output of the high-side gate driver |
42 | INLA | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver |
43 | INHB | I | High-side gate driver control input. This pin controls the output of the high-side gate driver |
44 | INLB | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver |
45 | INHC | I | High-side gate driver control input. This pin controls the output of the high-side gate driver |
46 | INLC | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver |
47 | PGND | PWR | Device power ground. Connect to system ground |
48 | NC | NC | No connect. Do not connect anything to this pin |
— | Thermal Pad | PWR | Must be connected to ground |