SLVSHQ2 December   2024 DRV8351-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three BLDC Gate Drivers
        1. 7.3.1.1 Gate Driver Timings
          1. 7.3.1.1.1 Propagation Delay
          2. 7.3.1.1.2 Deadtime and Cross-Conduction Prevention
        2. 7.3.1.2 Mode (Inverting and non inverting INLx)
      2. 7.3.2 Pin Diagrams
      3. 7.3.3 Gate Driver Protective Circuits
        1. 7.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
        2. 7.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DRV8351-SEP DRV8351-SEPD, DRV8351-SEPDI Package20-Pin TSSOPTop View Figure 5-1 DRV8351-SEPD, DRV8351-SEPDI Package20-Pin TSSOPTop View
Table 5-1 Pin Functions—20-Pin DRV8351-SEP Devices
PIN TYPE1 DESCRIPTION
NAME NO.
BSTA 20 O Bootstrap output pin. Connect capacitor between BSTA and SHA
BSTB 17 O Bootstrap output pin. Connect capacitor between BSTB and SHB
BSTC 14 O Bootstrap output pin. Connect capacitor between BSTC and SHC
GHA 19 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 13 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 11 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 9 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
INHA 1 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 2 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 3 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 4 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 5 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 6 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
GND 8 PWR Device ground.
SHA 18 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 15 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 12 I High-side source sense input. Connect to the high-side power MOSFET source.
GVDD 7 PWR Gate driver power supply input. Connect a X5R or X7R, GVDD-rated ceramic and greater then or equal to 10-uF local capacitance between the GVDD and GND pins.
  1. PWR = power, I = input, O = output, NC = no connection