SLVSHQ2 December   2024 DRV8351-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three BLDC Gate Drivers
        1. 7.3.1.1 Gate Driver Timings
          1. 7.3.1.1.1 Propagation Delay
          2. 7.3.1.1.2 Deadtime and Cross-Conduction Prevention
        2. 7.3.1.2 Mode (Inverting and non inverting INLx)
      2. 7.3.2 Pin Diagrams
      3. 7.3.3 Gate Driver Protective Circuits
        1. 7.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
        2. 7.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

4.8 V ≤ VGVDD ≤ 20 V, –55°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (GVDD, BSTx)
IGVDD GVDD standby mode current  INHx = INLX = 0; VBSTx = VGVDD 400 800 1500 µA
GVDD active mode current  INHx = INLX = Switching @20kHz; VBSTx = VGVDD; NO FETs connected 400 825 1500 µA
ILBSx Bootstrap pin leakage current VBSTx = VSHx = 40V; VGVDD = 0V 2 7 13 µA
ILBS_TRAN Bootstrap pin active mode transient leakage current  INHx = Switching@20kHz 30 105 220 µA
ILBS_DC Bootstrap pin active mode leakage static current  INHx = High 30 85 150 µA
ILSHx High-side source pin leakage current  INHx = INLX = 0; VBSTx - VSHx = 12V; VSHx = 0 to 40V 30 55 90 µA
LOGIC-LEVEL INPUTS (INHx, INLx, MODE)
VIL Input logic low voltage INLx, INHx pins 0.8 V
VHYS Input hysteresis INLx, INHx pins 40 100 260 mV
IIL_INLx INLx Input logic low current VPIN (Pin Voltage) = 0 V; INLx in non-inverting mode -1 0 1 µA
IIH_INLx INLx Input logic high current VPIN (Pin Voltage) = 5 V; INLx in non-inverting mode 5 20 30 µA
IIL INHx Input logic low current VPIN (Pin Voltage) = 0 V;  -1 0 1 µA
IIH INHx Input logic high current VPIN (Pin Voltage) = 5 V;  5 20 30 µA
RPD_INHx INHx Input pulldown resistance To GND 120 200 280 kΩ
RPD_INLx INLx Input pulldown resistance To GND, INLx in non-inverting mode 120 200 280 kΩ
RPD_MODE MODE Input pulldown resistance To GND 120 200 280 kΩ
GATE DRIVERS (GHx, GLx, SHx, SLx)
VGHx_LO High-side gate drive low level voltage IGLx = -100 mA; VGVDD = 12V; No FETs connected 0 0.15 0.35 V
VGHx_HI High-side gate drive high level voltage (VBSTx - VGHx) IGHx = 100 mA; VGVDD = 12V; No FETs connected 0.3 0.6 1.2 V
VGLx_LO Low-side gate drive low level voltage IGLx = -100 mA; VGVDD = 12V; No FETs connected 0 0.15 0.35 V
VGLx_HI Low-side gate drive high level voltage (VGVDD - VGHx) IGHx = 100 mA; VGVDD = 12V; No FETs connected 0.3 0.6 1.2 V
IDRIVEP_HS High-side peak source gate current GHx-SHx = 12V  400 750 1200 mA
IDRIVEN_HS High-side peak sink gate current GHx-SHx = 0V  850 1500 2100 mA
IDRIVEP_LS Low-side peak source gate current GLx = 12V  400 750 1200 mA
IDRIVEN_LS Low-side peak sink gate current GLx = 0V  850 1500 2100 mA
tPD Input to output propagation delay INHx, INLx to GHx, GLx; VGVDD  = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx 70 125 180 ns
tPD_match Matching propagation delay per phase GHx turning OFF to GLx turning ON, GLx turning OFF to GHx turning ON; VGVDD  = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx -30 ±4 30 ns
tPD_match Matching propagation delay phase to phase GHx/GLx turning ON to GHy/GLy turning ON, GHx/GLx turning OFF to GHy/GLy turning OFF;  VGVDD  = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx -30 ±4 30 ns
tR_GLx GLx rise time (10% to 90%) CLOAD = 1000 pF;  VGVDD  = VBSTx - VSHx > 8V; SHx = 0V 10 24 50 ns
tR_GHx GHx rise time (10% to 90%) CLOAD = 1000 pF;  VGVDD  = VBSTx - VSHx > 8V; SHx = 0V 10 24 50 ns
tF_GLx GLx fall time (90% to 10%) CLOAD = 1000 pF; VGVDD  = VBSTx - VSHx > 8V; SHx = 0V 5 12 30 ns
tF_GHx GHx fall time (90% to 10%) CLOAD = 1000 pF; VGVDD  = VBSTx - VSHx > 8V; SHx = 0V 5 12 30 ns
tDEAD Gate drive dead time 150 215 280 ns
tPW_MIN Minimum input pulse width on INHx, INLx that changes the output on GHx, GLx 40 70 150 ns
BOOTSTRAP DIODES
VBOOTD Bootstrap diode forward voltage IBOOT = 100 µA 0.45 0.7 0.85 V
IBOOT = 100 mA 2 2.3 3.1 V
RBOOTD Bootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT) IBOOT = 100 mA and 80 mA 11 15 25 Ω
PROTECTION CIRCUITS
VGVDDUV Gate Driver Supply undervoltage lockout (GVDDUV) Supply rising 4.45 4.6 4.7 V
Supply falling 4.2 4.35 4.4 V
VGVDDUV_HYS Gate Driver Supply UV hysteresis Rising to falling threshold 250 280 310 mV
tGVDDUV Gate Driver Supply undervoltage deglitch time 5 10 13 µs
VBSTUV Boot Strap undervoltage lockout (VBSTx - VSHx) Supply rising 3.6 4.2 4.8 V
Boot Strap undervoltage lockout (VBSTx - VSHx) Supply falling 3.5 4 4.5 V
VBSTUV_HYS Bootstrap UV hysteresis Rising to falling threshold 200 mV
tBSTUV Bootstrap undervoltage deglitch time 6 10 22 µs