SLOSE51A June   2020  – December 2020 DRV8428E

ADVANCE INFORMATION  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Drivers
      2. 7.3.2 Bridge Control
      3. 7.3.3 Current Regulation, Off-time and Decay Modes
        1. 7.3.3.1 Mixed Decay
        2. 7.3.3.2 Smart tune Dynamic Decay
        3. 7.3.3.3 Smart tune Ripple Control
        4. 7.3.3.4 Blanking time
      4. 7.3.4 Linear Voltage Regulators
      5. 7.3.5 Logic and Seven-Level Pin Diagrams
      6. 7.3.6 Protection Circuits
        1. 7.3.6.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.6.2 Overcurrent Protection (OCP)
        3. 7.3.6.3 Thermal Shutdown (OTSD)
        4. 7.3.6.4 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Operating Mode (nSLEEP = 1)
      3. 7.4.3 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Regulation
        2. 8.2.2.2 Power Dissipation and Thermal Calculation
          1. 8.2.2.2.1 Application Curves
    3. 8.3 Alternate Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Current Regulation
          1. 8.3.2.1.1 Stepper Motor Speed
            1. 8.3.2.1.1.1 Decay Modes
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 Logic and Seven-Level Pin Diagrams

Figure 7-10 gives the input structure for logic-level pins APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2 and nSLEEP:

GUID-1ECA61DE-3EFF-46A3-9F8A-F79D710C97B8-low.gifFigure 7-10 Logic-level Input Pin Diagram

Seven-level logic pin DECAY/TOFF has the following structure as shown in Figure 7-11.

GUID-740375A3-632F-4542-8941-320E68D770EC-low.gifFigure 7-11 Seven-Level Input Pin Diagram