SLOSE51A June   2020  – December 2020 DRV8428E

ADVANCE INFORMATION  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Drivers
      2. 7.3.2 Bridge Control
      3. 7.3.3 Current Regulation, Off-time and Decay Modes
        1. 7.3.3.1 Mixed Decay
        2. 7.3.3.2 Smart tune Dynamic Decay
        3. 7.3.3.3 Smart tune Ripple Control
        4. 7.3.3.4 Blanking time
      4. 7.3.4 Linear Voltage Regulators
      5. 7.3.5 Logic and Seven-Level Pin Diagrams
      6. 7.3.6 Protection Circuits
        1. 7.3.6.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.6.2 Overcurrent Protection (OCP)
        3. 7.3.6.3 Thermal Shutdown (OTSD)
        4. 7.3.6.4 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Operating Mode (nSLEEP = 1)
      3. 7.4.3 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Regulation
        2. 8.2.2.2 Power Dissipation and Thermal Calculation
          1. 8.2.2.2.1 Application Curves
    3. 8.3 Alternate Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Current Regulation
          1. 8.3.2.1.1 Stepper Motor Speed
            1. 8.3.2.1.1.1 Decay Modes
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Current Regulation, Off-time and Decay Modes

During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 7-5, Item 1.

The current through the motor windings is regulated by an adjustable, off-time PWM current-regulation circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage, inductance of the winding, and the magnitude of the back EMF present. When the current hits the current regulation threshold, the bridge enters a decay mode for a period of time determined by the seven-level DECAY/TOFF pin setting to decrease the current. After the off-time expires, the bridge is re-enabled, starting another PWM cycle.

Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay. In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. The opposite FETs are turned on; as the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 7-5, item 2. In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown in Figure 7-5, Item 3.

The PWM chopping current is set by a comparator which monitors the voltage across the current sense MOSFETs in parallel with the low-side power MOSFETs. To generate the reference voltage for the current chopping comparator, the VREFx input is attenuated by a factor of Kv.

The chopping current (IFS) can be calculated as IFS (A) = VREFx (V) / KV (V/A) = VREFx (V) / 3 (V/A).

GUID-18AEE5D7-6CD1-4C1D-ABFA-643A18D2A4EB-low.gifFigure 7-5 Decay Modes

The decay mode and off time for each bridge is selected by setting the seven-level DECAY/TOFF pin as shown in Table 7-4.

Table 7-4 Decay Mode Settings
DECAY/TOFFDECAY MODEOFF TIME
0Smart tune Ripple Control-
14.7kΩ to GNDMixed 30% Decay7µs
44.2kΩ to GND16µs
100kΩ to GND32µs
249kΩ to GNDSmart tune Dynamic Decay7µs
Hi-Z16µs
DVDD32µs