SLOSE79B August 2022 – October 2023 DRV8462
PRODUCTION DATA
The current through the motor windings is regulated by a PWM current-regulation circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the supply voltage, inductance of the winding, and the magnitude of the back EMF present. When the current hits the current regulation threshold, the bridge enters a decay mode for the OFF time to decrease the current, as shown in 9. After the off-time expires, the bridge is re-enabled, starting another PWM cycle.
The PWM regulation current is set by a comparator which monitors the voltage across the current sense MOSFETs in parallel with the low-side power MOSFETs. When the device is configured with H/W interface, the current sense MOSFETs are biased with a reference current that is the output of a current-mode sine-weighted DAC whose full-scale reference current is set by the voltage at the VREF pin. When operating with SPI interface, two registers (TRQ_DAC and ISTSL) can further scale the reference current.
Use Equation 15 to calculate the full-scale regulation current for H/W interface.
For the SPI interface, the 8-bit TRQ_DAC register further scales the full-scale current as shown in Equation 15. See Table 7-16 for TRQ_DAC settings.
TRQ_DAC | CURRENT SCALAR |
---|---|
11111111b (default) | 100% |
11111110b | 99.61% |
11111101b | 99.22% |
11111100b | 98.83% |
........ | ........ |
00000000b | 0.39% |
Another 8-bit register ISTSL programs the holding current (IHOLD) when STEP pulses are not applied and the motor is being held at same position. Transitioning to a lower value of holding current reduces motor and driver power loss. See Standstill Power Saving Mode for details.
ISTSL | Holding Current Value |
---|---|
11111111b | 100% |
11111110b | 99.61% |
11111101b | 99.22% |
11111110b | 98.83% |
........ | ........ |
10000000b (default) | 50.39% |
........ | ........ |
00000000b | 0.39% |