SLVSDR9E October   2016  – January 2021 DRV8702-Q1 , DRV8703-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8.     15
    9. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bridge Control
        1. 7.3.1.1 Logic Tables
      2. 7.3.2  MODE Pin
      3. 7.3.3  nFAULT Pin
      4. 7.3.4  Current Regulation
      5. 7.3.5  Amplifier Output (SO)
        1. 7.3.5.1 SO Sample and Hold Operation
      6. 7.3.6  PWM Motor Gate Drivers
        1. 7.3.6.1 Miller Charge (QGD)
      7. 7.3.7  IDRIVE Pin (DRV8702-Q1 Only)
      8. 7.3.8  Dead Time
      9. 7.3.9  Propagation Delay
      10. 7.3.10 Overcurrent VDS Monitor
      11. 7.3.11 VDS Pin (DRV8702-Q1 Only)
      12. 7.3.12 Charge Pump
      13. 7.3.13 Gate Drive Clamp
      14. 7.3.14 Protection Circuits
        1. 7.3.14.1 VM Undervoltage Lockout (UVLO2)
        2. 7.3.14.2 Logic Undervoltage (UVLO1)
        3. 7.3.14.3 VCP Undervoltage Lockout (CPUV)
        4. 7.3.14.4 Overcurrent Protection (OCP)
        5. 7.3.14.5 Gate Driver Fault (GDF)
        6. 7.3.14.6 Thermal Shutdown (TSD)
        7. 7.3.14.7 Watchdog Fault (WDFLT, DRV8703-Q1 Only)
        8. 7.3.14.8 Reverse Supply Protection
      15. 7.3.15 Hardware Interface
        1. 7.3.15.1 IDRIVE (6-level input)
        2. 7.3.15.2 VDS (6-Level Input)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 Serial Peripheral Interface (SPI)
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 VDS Configuration
        4. 8.2.2.4 Current Chopping Configuration
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES (VM, AVDD, DVDD)
VVMVM operating voltageGate drivers functional5.545V
Logic functional4.545
IVMVM operating supply currentVVM = 13.5 V; nSLEEP=15.57.512mA
I(SLEEP)VM sleep mode supply currentnSLEEP = 0, VVM = 13.5 V, TA = 25°C14µA
nSLEEP = 0, VVM = 13.5 V, TA = 125°C(1)25
VDVDDInternal logic regulator voltage2-mA load33.33.5V
30-mA load, VVM = 13.5 V2.93.23.5
VAVDDInternal logic regulator voltage2-mA load4.755.3V
30-mA load, VVM = 13.5 V4.655.3
CHARGE PUMP (VCP, CPH, CPL)
VVCPVCP operating voltageVVM = 13.5 V; IVCP = 0 to 12 mA22.523.524.5V
VVM = 8 V; IVCP = 0 to 10 mA13.71414.8
VVM = 5.5 V; IVCP = 0 to 8 mA8.99.19.5
IVCPCharge-pump current capacityVVM > 13.5 V12mA
8 V < VVM < 13.5 V10
5.5 V < VVM < 8 V8
CONTROL INPUTS (IN1/PH, IN2/EN, nSLEEP, MODE, nSCS, SCLK, SDI)
VILInput logic-low voltage00.8V
VIHInput logic-high voltage1.55.25V
VhysInput logic hysteresis100mV
IILInput logic-low currentVIN = 0 V–55µA
IIHInput logic-high currentVIN = 5 V70µA
RPDPulldown resistanceIN1/PH, IN2/EN, nSLEEP, nSCS, SCLK, SDI64100173kΩ
RPDPulldown resistanceMODE65kΩ
RPUPullup ResistanceMODE26kΩ
CONTROL OUTPUTS (nFAULT, WDFAULT, SDO)
VOLOutput logic-low voltageIO = 2 mA0.1V
IOZOutput high-impedance leakage5V pullup voltage-22µA
FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)
VGSHHigh-side VGS gate drive (gate-to-source)VVM > 13.5 V; VGSH with respect to SHx10.511.5V
VVM = 8 V; VGSH with respect to SHx5.76.8
VVM = 5.5 V; VGSH with respect to SHx3.44
VGSLLow-side VGS gate drive (gate-to-source)VVM > 10.5 V10.5V
VVM < 10.5 VVVM – 2
IDRIVE(SRC_HS)High-side peak source current
(VVM = 5.5V)		R(IDRIVE) < 1kΩ to GND (DRV8702) or IDRIVE = 3’b000 (DRV8703)10mA
R(IDRIVE) = 33kΩ to GND (DRV8702) or IDRIVE = 3’b001 (DRV8703)20
R(IDRIVE) = 200kΩ to GND (DRV8702) or IDRIVE = 3’b010 (DRV8703)50
IDRIVE = 3’b011 (DRV8703)70
IDRIVE = 3’b100 (DRV8703)100
R(IDRIVE) > 2MΩ to GND (DRV8702) or IDRIVE = 3’b101 (DRV8703)145
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or IDRIVE = 3’b110 (DRV8703)190
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or IDRIVE = 3’b111 (DRV8703)240
IDRIVE(SNK_HS)High-side peak sink current
(VVM = 5.5V)		R(IDRIVE) < 1kΩ to GND (DRV8702) or IDRIVE = 3’b000 (DRV8703)20mA
R(IDRIVE) = 33kΩ to GND (DRV8702) or IDRIVE = 3’b001 (DRV8703)40
R(IDRIVE) = 200kΩ to GND (DRV8702) or IDRIVE = 3’b010 (DRV8703)90
IDRIVE = 3’b011 (DRV8703)120
IDRIVE = 3’b100 (DRV8703)170
R(IDRIVE) > 2MΩ to GND (DRV8702) or IDRIVE = 3’b101 (DRV8703)250
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or IDRIVE = 3’b110 (DRV8703)330
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or IDRIVE = 3’b111 (DRV8703)420
IDRIVE(SRC_LS)Low-side peak source current
(VVM = 5.5V)		R(IDRIVE) < 1kΩ to GND (DRV8702) or IDRIVE = 3’b000 (DRV8703)10mA
R(IDRIVE) = 33kΩ to GND (DRV8702) or IDRIVE = 3’b001 (DRV8703)20
R(IDRIVE) = 200kΩ to GND (DRV8702) or IDRIVE = 3’b010 (DRV8703)40
IDRIVE = 3’b011 (DRV8703)55
IDRIVE = 3’b100 (DRV8703)75
R(IDRIVE) > 2MΩ to GND (DRV8702) or IDRIVE = 3’b101 (DRV8703)115
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or IDRIVE = 3’b110 (DRV8703)145
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or IDRIVE = 3’b111 (DRV8703)190
IDRIVE(SNK_LS)Low-side peak sink current
(VVM = 5.5V)		R(IDRIVE) < 1kΩ to GND (DRV8702) or IDRIVE = 3’b000 (DRV8703)20mA
R(IDRIVE) = 33kΩ to GND (DRV8702) or IDRIVE = 3’b001 (DRV8703)40
R(IDRIVE) = 200kΩ to GND (DRV8702) or IDRIVE = 3’b010 (DRV8703)85
IDRIVE = 3’b011 (DRV8703)115
IDRIVE = 3’b100 (DRV8703)160
R(IDRIVE) > 2MΩ to GND (DRV8702) or IDRIVE = 3’b101 (DRV8703)235
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or IDRIVE = 3’b110 (DRV8703)300
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or IDRIVE = 3’b111 (DRV8703)360
IDRIVE(SRC_HS)High-side peak source current
(VVM = 13.5V)		R(IDRIVE) < 1kΩ to GND (DRV8702) or IDRIVE = 3’b000 (DRV8703)10mA
R(IDRIVE) = 33kΩ to GND (DRV8702) or IDRIVE = 3’b001 (DRV8703)20
R(IDRIVE) = 200kΩ to GND (DRV8702) or IDRIVE = 3’b010 (DRV8703)50
IDRIVE = 3’b011 (DRV8703)70
IDRIVE = 3’b100 (DRV8703)105
R(IDRIVE) > 2MΩ to GND (DRV8702) or IDRIVE = 3’b101 (DRV8703)155
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or IDRIVE = 3’b110 (DRV8703)210
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or IDRIVE = 3’b111 (DRV8703)260
IDRIVE(SNK_HS)High-side peak sink current
(VVM = 13.5V)		R(IDRIVE) < 1kΩ to GND (DRV8702) or IDRIVE = 3’b000 (DRV8703)20mA
R(IDRIVE) = 33kΩ to GND (DRV8702) or IDRIVE = 3’b001 (DRV8703)40
R(IDRIVE) = 200kΩ to GND (DRV8702) or IDRIVE = 3’b010 (DRV8703)95
IDRIVE = 3’b011 (DRV8703)130
IDRIVE = 3’b100 (DRV8703)185
R(IDRIVE) > 2MΩ to GND (DRV8702) or IDRIVE = 3’b101 (DRV8703)265
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or IDRIVE = 3’b110 (DRV8703)350
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or IDRIVE = 3’b111 (DRV8703)440
IDRIVE(SRC_LS)Low-side peak source current
(VVM = 13.5V)		R(IDRIVE) < 1kΩ to GND (DRV8702) or IDRIVE = 3’b000 (DRV8703)10mA
R(IDRIVE) = 33kΩ to GND (DRV8702) or IDRIVE = 3’b001 (DRV8703)20
R(IDRIVE) = 200kΩ to GND (DRV8702) or IDRIVE = 3’b010 (DRV8703)45
IDRIVE = 3’b011 (DRV8703)60
IDRIVE = 3’b100 (DRV8703)90
R(IDRIVE) > 2MΩ to GND (DRV8702) or IDRIVE = 3’b101 (DRV8703)130
R(IDRIVE) = 68kΩ to AVDD (DRV8702) or IDRIVE = 3’b110 (DRV8703)180
R(IDRIVE) = 1kΩ to AVDD (DRV8702) or IDRIVE = 3’b111 (DRV8703)225
IDRIVE(SNK_LS)Low-side peak sink current
(VVM = 13.5V)		R(IDRIVE) < 1kΩ to GND (DRV8702-Q1) or IDRIVE = 3’b000 (DRV8703-Q1)20mA
R(IDRIVE) = 33 kΩ to GND (DRV8702-Q1) or IDRIVE = 3’b001 (DRV8703-Q1)40
R(IDRIVE) = 200 kΩ to GND (DRV8702-Q1) or IDRIVE = 3’b010 (DRV8703-Q1)95
IDRIVE = 3’b011 (DRV8703-Q1)125
IDRIVE = 3’b100 (DRV8703-Q1)180
R(IDRIVE) > 2 MΩ to GND (DRV8702-Q1) or IDRIVE = 3’b101 (DRV8703-Q1)260
R(IDRIVE) = 68 kΩ to AVDD (DRV8702-Q1) or IDRIVE = 3’b110 (DRV8703-Q1)350
R(IDRIVE) = 1 kΩ to AVDD (DRV8702-Q1) or IDRIVE = 3’b111 (DRV8703-Q1)430
IHOLDFET holding currentSource current after tDRIVE10mA
Sink current after tDRIVE40
ISTRONGFET holdoff strong pulldownGHx750mA
GLx1000
R(OFF)FET gate holdoff resistorPulldown GHx to SHx150kΩ
Pulldown GLx to GND150
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
VVREFVREF input rms voltageFor current internal chopping0.3(2)3.6V
RVREFVREF input impedanceDRV8702-Q1 and DRV8703-Q1 VREF_SCL = 00 (100%)1MΩ
DRV8703-Q1 VREF_SCL = 2’b01, 2’b10 or 2’b11175kΩ
AVAmplifier gain (DRV8702-Q1)60 < VSP < 225 mV; VSN = GND19.319.820.3V/V
AVAmplifier gain (DRV8703-Q1)GAIN_CS = 00; 10 < VSP < 450 mV; VSN = GND9.751010.25V/V
GAIN_CS = 01; 60 < VSP < 225 mV; VSN = GND19.319.820.3
GAIN_CS = 10; 10 < VSP < 112 mV; VSN = GND38.439.440.4
GAIN_CS = 11; 10 < VSP < 56 mV; VSN = GND737881
VIOInput-referred offsetVSP = VSN = GND510mV
VIO(DRIFT)Drift offset(2)VSP = VSN = GND10µV/°C
ISPSP input currentVSP = 100 mV; VSN = GND–20µA
VSOSO pin output voltage rangeAV × Vio4.5V
C(SO)Allowable SO pin capacitance1nF
PROTECTION CIRCUITS
V(UVLO2)VM undervoltage lockoutVM falling; UVLO2 report5.255.45V
VM rising; UVLO2 recovery5.45.65
V(UVLO1)Logic undervoltage lockout4.5V
Vhys(UVLO)VM undervoltage hysteresisRising to falling threshold100mV
V(CP_UV)Charge pump undervoltageVCP falling; CPUV reportVVM + 1.5V
VCP rising; CPUV recoveryVVM + 1.55
Vhys(CP_UV)CP undervoltage hysteresisRising to falling threshold50mV
VDS(OCP)Overcurrent protection trip level, VDS of each external FET (DRV8702-Q1)
High side FETs: VDRAIN – SHx
Low side FETs: SHx – SP/SL2		R(VDS) < 1 kΩ to GND0.06V
R(VDS) = 33 kΩ to GND0.12
R(VDS) = 200 kΩ to GND0.24
R(VDS) > 2 MΩ to GND0.48
R(VDS) = 68 kΩ to AVDD0.96
R(VDS) < 1 kΩ to AVDDDisabled
VDS(OCP)Overcurrent protection trip level, VDS of each external FET (DRV8703-Q1)
High-side FETs: VDRAIN – SHx
Low-side FETs: SHx – SP/SL2		VDS_LEVEL = 3’b0000.06V
VDS_LEVEL = 3’b0010.145
VDS_LEVEL = 3’b0100.17
VDS_LEVEL = 3’b0110.2
VDS_LEVEL = 3’b1000.12
VDS_LEVEL = 3’b1010.24
VDS_LEVEL = 3’b1100.48
VDS_LEVEL = 3’b1110.96
VSP(OCP)Overcurrent protection trip level, measured by sense amplifierVSP with respect to GND0.811.2V
T(OTW)Thermal warning temperature(1)Die temperature TJ120135145°C
TSDThermal shutdown temperature(1)Die temperature TJ150°C
ThysThermal shutdown hysteresis(1)Die temperature TJ20°C
VC(GS)Gate-drive clamping voltagePositive clamping voltage16.31717.8V
Negative clamping voltage–1–0.7–0.5
(1) Ensured by design and characterization data.
(2) Operational at VVREF = 0 to approximately 0.3 V, but accuracy is degraded.