SLLSFB6B May 2020 – May 2024 DRV8705-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The DRV8705-Q1 provides a dedicated driver disable with the DRVOFF pin. When DRVOFF is asserted, it will enable the gate driver pull downs regardless of the pin or SPI inputs.
On SPI device variants, the EN_DRV function is provide for a controlled power up sequence. After device power up the gate drivers remain disabled until the EN_DRV register bit is asserted. This allows for the system to power up and conduct configuration sequences before the gate drivers are enabled. On H/W devices, this functionality is not provided and the driver will automatically enable after power up.