SLLSFB6B May 2020 – May 2024 DRV8705-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
If the VGS voltage does not cross the the VGS_LVL comparator level for longer than the tDRIVE time, the DRV8705-Q1 detects a VGS gate fault condition. Additionally, in independent half-bridge and split HS/LS PWM control (BRG_MODE = 00b, 11b) the device can be configured to disable all half-bridges or only the associated half-bridge in which the gate fault occurred through the VGS_IND register setting.
On SPI device variants, the VGS gate fault monitor can respond and recover in four different modes set through the VGS_MODE register setting.
On H/W device variants, the VGS gate fault mode is fixed to cycle by cycle and tDRIVE is fixed to 4 µs. Independent half-bridge shutdown is automatically enabled for the independent half-bridge and split HS/LS PWM control modes. Additionally, the VGS gate fault protection can be disabled through level 6 of the VDS pin multi-level input.