SLLSFB6B May   2020  – May 2024 DRV8705-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Descriptions
  5.   Device Comparison Table
  6. 4 Pin Configuration
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 External Components
      2. 6.3.2 Device Interface Variants
        1. 6.3.2.1 Serial Peripheral Interface (SPI)
        2. 6.3.2.2 Hardware (H/W)
      3. 6.3.3 Input PWM Modes
        1. 6.3.3.1 Half-Bridge Control
        2. 6.3.3.2 H-Bridge Control
        3. 6.3.3.3 Split HS and LS Solenoid Control
      4. 6.3.4 Smart Gate Driver
        1. 6.3.4.1 Functional Block Diagram
        2. 6.3.4.2 Slew Rate Control (IDRIVE)
        3. 6.3.4.3 Gate Drive State Machine (TDRIVE)
      5. 6.3.5 Doubler (Single-Stage) Charge Pump
      6. 6.3.6 Low-Side Differential Current Shunt Amplifier
      7. 6.3.7 Pin Diagrams
        1. 6.3.7.1 Logic Level Input Pin (DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, nSCS, SCLK, SDI)
        2. 6.3.7.2 Logic Level Push Pull Output (SDO)
        3. 6.3.7.3 Logic Level Open Drain Output (nFAULT)
        4. 6.3.7.4 Quad-Level Input (GAIN)
        5. 6.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 6.3.8 Protection and Diagnostics
        1. 6.3.8.1  Gate Driver Disable and Enable (DRVOFF and EN_DRV)
        2. 6.3.8.2  Fault Reset (CLR_FLT)
        3. 6.3.8.3  DVDD Logic Supply Power on Reset (DVDD_POR)
        4. 6.3.8.4  PVDD Supply Undervoltage Monitor (PVDD_UV)
        5. 6.3.8.5  PVDD Supply Overvoltage Monitor (PVDD_OV)
        6. 6.3.8.6  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        7. 6.3.8.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 6.3.8.8  Gate Driver Fault (VGS_GDF)
        9. 6.3.8.9  Thermal Warning (OTW)
        10. 6.3.8.10 Thermal Shutdown (OTSD)
        11. 6.3.8.11 Offline Short Circuit and Open Load Detection (OOL and OSC)
        12. 6.3.8.12 Fault Detection and Response Summary Table
    4. 6.4 Device Function Modes
      1. 6.4.1 Inactive or Sleep State
      2. 6.4.2 Standby State
      3. 6.4.3 Operating State
    5. 6.5 Programming
      1. 6.5.1 SPI Interface
      2. 6.5.2 SPI Format
      3. 6.5.3 SPI Interface for Multiple Slaves
        1. 6.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
  9. 7 Register Maps
    1. 7.1 STATUS Registers
    2. 7.2 CONTROL Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Driver Configuration
          1. 8.2.2.1.1 VCP Load Calculation Example
          2. 8.2.2.1.2 IDRIVE Calculation Example
        2. 8.2.2.2 Current Shunt Amplifier Configuration
        3. 8.2.2.3 Power Dissipation
  11. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  12. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  14. 12Revision History
  15. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration

DRV8705-Q1 DRV8705S-Q1 RHB Package32-Pin VQFNTop ViewFigure 4-1 DRV8705S-Q1 RHB Package32-Pin VQFNTop View
DRV8705-Q1 DRV8705H-Q1 RHB Package32-Pin VQFNTop ViewFigure 4-2 DRV8705H-Q1 RHB Package32-Pin VQFNTop View
Table 4-1 DRV8705-Q1_RHB Package (VQFN) Pin Functions
PIN I/O TYPE DESCRIPTION
NO. NAME NAME
DRV8705S-Q1 DRV8705H-Q1
1 GND I/O Ground Device ground. Connect to system ground.
2 DVDD I Power Device logic and digital output power supply input. Connect a 1.0µF, 6.3V ceramic capacitor between the DVDD and GND pins.
3 nSCS — I Digital Serial chip select. A logic low on this pin enables serial interface communication. Internal pullup resistor.
— GAIN I Analog Amplifier gain setting. 4 level input pin set by an external resistor.
4 SCLK — I Digital Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pulldown resistor.
— VDS I Analog VDS monitor threshold setting. 6 level input pin set by an external resistor.
5 SDI — I Digital Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pulldown resistor.
— IDRIVE I Analog Gate driver output current setting. 6 level input pin set by an external resistor.
6 SDO — O Digital Serial data output. Data is shifted out on the rising edge of the SCLK pin. Push-pull output.
— MODE I Analog PWM input mode setting. 4 level input pin set by an external resistor.
7 IN1/EN I Digital Half-bridge control input. See PWM modes for details. Internal pulldown.
8 nHIZ1 I Digital Half-bridge control input. See PWM modes for details. Internal pulldown.
9 IN2/PH I Digital Half-bridge control input. See PWM modes for details. Internal pulldown.
10 nHIZ2 I Digital Half-bridge control input. See PWM modes for details. Internal pulldown.
11 nSLEEP I Digital Device enable pin. Logic low to shutdown the device and enter sleep mode. Internal pulldown resistor.
12 DRVOFF I Digital Driver shutdown pin. Logic high to pull down both high-side and low-side gate driver output. Internal pulldown resistor.
13 nFAULT O Digital Fault indicator output. This pin is pulled logic low to indicate a fault condition. Open-drain output. Requires external pullup resistor.
14 SO O Analog Shunt amplifier output.
15 RSVD — — Reserved. Connect to ground or leave disconnected.
16 AREF I Power External voltage reference and power supply for current sense amplifiers. Connect a 0.1µF, 6.3V ceramic capacitor between the AREF and AGND pins.
17 AGND I/O Power Device ground. Connect to system ground.
18 SP I Analog Shunt amplifier positive input. Connect to positive terminal of the current shunt resistor.
19 SN I Analog Shunt amplifier negative input. Connect to negative terminal of the current shunt resistor.
20 GH1 O Analog High-side gate driver output. Connect to the gate of the high-side power MOSFET.
21 SH1 I Analog High-side source sense input. Connect to the high-side power MOSFET source.
22 GL1 O Analog Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
23 SL1 I Analog Low-side MOSFET gate drive sense and power return. Connect to system ground with low impedance path to the low-side MOSFET ground return.
24 SL2 I Analog Low-side MOSFET gate drive sense and power return. Connect to system ground with low impedance path to the low-side MOSFET ground return.
25 GL2 O Analog Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
26 SH2 I Analog High-side source sense input. Connect to the high-side power MOSFET source.
27 GH2 O Analog High-side gate driver output. Connect to the gate of the high-side power MOSFET.
28 DRAIN I Analog Bridge MOSFET drain voltage sense pin. Connect to common point of the high-side MOSFET drains.
29 PVDD I Power Device driver power supply input. Connect to the bridge power supply. Connect a 0.1µF, PVDD-rated ceramic capacitor and local bulk capacitance greater than or equal to 10µF between PVDD and GND pins.
30 VCP I/O Power Charge pump output. Connect a 1µF, 16V ceramic capacitor between the VCP and PVDD pins.
31 CPH I/O Power Charge pump switching node. Connect a 100nF, PVDD-rated ceramic capacitor between the CPH and CPL pins.
32 CPL I/O Power Charge pump switching node. Connect a 100nF, PVDD-rated ceramic capacitor between the CPH and CPL pins.