SLLSFB6B May 2020 – May 2024 DRV8705-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLIES (DRAIN, DVDD, PVDD, VCP) | ||||||
IPVDDQ | PVDD sleep mode current | VPVDD, VDRAIN = 13.5V, nSLEEP = 0V –40 ≤ TJ ≤ 85°C No External MOSFETs |
2.25 | 3 | µA | |
IDRAINQ | DRAIN sleep mode current | VPVDD, VDRAIN = 13.5V, nSLEEP = 0V –40 ≤ TJ ≤ 85°C No External MOSFETs |
2 | 2.75 | µA | |
IDVDDQ | DVDD sleep mode current | VPVDD, VDRAIN = 13.5V, nSLEEP = 0V –40 ≤ TJ ≤ 85°C No External MOSFETs |
2 | 3.5 | µA | |
IPVDD | PVDD active mode current | VPVDD, VDRAIN = 13.5V, nSLEEP = 5V No External MOSFETs |
2 | 3 | mA | |
IDRAIN | DRAIN active mode current | VPVDD, VDRAIN = 13.5V, nSLEEP = 5V,
VDS_LVL ≤ 500mV No External MOSFETs |
250 | 325 | µA | |
IDVDD | DVDD active mode current | VDVDD = 5V, SDO = 0V No External MOSFETs |
3.5 | 5.5 | mA | |
fDVDD | Digital oscilator switching frequency | Primary frequency of spread spectrum. | 14.25 | MHz | ||
tWAKE | Turnon time | nSLEEP = 5 V to active mode | 1 | ms | ||
tSLEEP | Turnoff time | nSLEEP = 0V to sleep mode | 1 | ms | ||
VVCP | Charge pump regulator voltage with respect to PVDD | VPVDD ≥ 13V, IVCP ≤ 15mA | 9.5 | 10.5 | 11 | V |
VPVDD = 11V, IVCP ≤ 15mA | 8.4 | 10 | 11 | |||
VPVDD = 9V, IVCP ≤ 11mA | 7 | 8 | 9 | |||
VPVDD = 7V, IVCP ≤ 7.5mA | 5.5 | 6 | 7 | |||
VPVDD = 5.5V, IVCP ≤ 5mA | 4.5 | 5 | 5.5 | |||
fVCP | Charge pump switching frequency | Primary frequency of spread spectrum. | 400 | kHz | ||
LOGIC-LEVEL INPUTS (DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, nSCS, SCLK, SDI) | ||||||
VIL | Input logic low voltage | DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, SCLK, SDI | 0 | VDVDD x 0.3 | V | |
VIH | Input logic high voltage | DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, SCLK, SDI | VDVDD x 0.7 | 5.5 | V | |
VHYS | Input hysteresis | VDVDD x 0.1 | V | |||
IIL | Input logic low current | VDIN = 0V, DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, SCLK, SDI | –5 | 5 | µA | |
VDIN = 0V, nSCS | 50 | 100 | ||||
IIH | Input logic high current | VDIN = 5V, DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, SCLK, SDI | 50 | 100 | µA | |
VDIN = 5V, VDVDD = 5V, nSCS | –5 | 5 | ||||
RPD | Input pulldown resistance | To GND, DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, SCLK, SDI | 50 | 100 | 150 | kΩ |
RPU | Input pullup resistance | To DVDD, nSCS | 50 | 100 | 150 | kΩ |
MULTI-LEVEL INPUTS (GAIN, IDRIVE, MODE, VDS) | ||||||
VQI1 | Quad-level input 1 | GAIN, MODE
Voltage to set level 1 |
0 | VDVDD x 0.1 | V | |
RQI2 | Quad-level input 2 | GAIN, MODE
Resistance to GND to set level 2 |
44.65 | 47 | 49.35 | kΩ |
RQI3 | Quad-level input 3 | GAIN, MODE
Resistance to GND to set level 3 |
500 | Hi-Z | kΩ | |
VQI4 | Quad-level input 4 | GAIN, MODE
Voltage to set level 4 |
VDVDD x 0.9 | 5.5 | V | |
RQPD | Quad-level pulldown resistane | GAIN, MODE, To GND | 98 | kΩ | ||
RQPU | Quad-level pullup resistane | GAIN, MODE, To DVDD | 98 | kΩ | ||
VSI1 | Six-level input 1 | IDRIVE, VDS Voltage to set level 1 |
0 | VDVDD x 0.1 | V | |
RSI2 | Six-level input 2 | IDRIVE, VDS Resistance to GND to set level 2 |
28.5 | 30 | 31.5 | kΩ |
RSI3 | Six-level input 3 | IDRIVE, VDS Resistance to GND to set level 3 |
95 | 100 | 105 | kΩ |
RSI4 | Six-level input 4 | IDRIVE, VDS Resistance to GND to set level 4 |
500 | Hi-Z | kΩ | |
RSI5 | Six-level input 5 | IDRIVE, VDS Resistance to DVDD to set level 5 |
58.9 | 62 | 65.1 | kΩ |
RSI6 | Six-level input 6 | IDRIVE, VDS Voltage to set level 6 |
VDVDD x 0.9 | 5.5 | V | |
RSPD | Six-level pulldown resistane | IDRIVE, VDS, To GND | 98 | kΩ | ||
RSPU | Six-level pullup resistane | IDRIVE, VDS To DVDD | 69 | kΩ | ||
LOGIC-LEVEL OUTPUTS (nFAULT, SDO) | ||||||
VOL | Output logic low voltage | IDOUT = 5mA | 0.5 | V | ||
VOH | Output logic high voltage | IDOUT = –5mA, SDO | VDVDD x 0.8 | V | ||
IODZ | Open-drain logic high current | VOD = 5V, nFAULT | –10 | 10 | µA | |
GATE DRIVERS (GHx, GLx) | ||||||
VGHx_L | GHx low level output voltage | IDRVN_HS = ISTRONG, IGHx = 1mA, GHx to SHx |
0 | 0.25 | V | |
VGLx_L | GLx low level output voltage | IDRVN_LS = ISTRONG, IGLx = 1mA, GLx to SLx |
0 | 0.25 | V | |
VGHx_H | GHx high level output voltage | IDRVP_HS = IHOLD, IGHx = 1mA, VCP to GHx |
0 | 0.25 | V | |
VGLx_H | GLx high level output voltage | IDRVP_LS = IHOLD, IGLx = 1mA, 10.5V ≤ VPVDD ≤ 37V, GLx to SLx |
10.25 | 10.5 | 12.5 | V |
IDRVP_LS = IHOLD, IGLx = 1mA, 4.9V ≤ VPVDD ≤ 10.5V, GLx to SLx |
VPVDD - 0.25 | VPVDD | VPVDD | V | ||
IDRVP, SPI | Peak gate current (source) SPI Device |
IDRVP = 0000b, VGSx = 3V, VPVDD ≥ 7V | 0.2 | 0.5 | 0.8 | mA |
IDRVP = 0001b, VGSx = 3V, VPVDD ≥ 7V | 0.5 | 1 | 1.5 | |||
IDRVP = 0010b, VGSx = 3V, VPVDD ≥ 7V | 1.3 | 2 | 2.7 | |||
IDRVP = 0011b, VGSx = 3V, VPVDD ≥ 7V | 2.1 | 3 | 3.9 | |||
IDRVP = 0100b, VGSx = 3V, VPVDD ≥ 7V | 2.9 | 4 | 5.1 | |||
IDRVP = 0101b, VGSx = 3V, VPVDD ≥ 7V | 4.5 | 6 | 7.5 | |||
IDRVP = 0110b, VGSx = 3V, VPVDD ≥ 7V | 6 | 8 | 10 | |||
IDRVP = 0111b, VGSx = 3V, VPVDD ≥ 7V | 9 | 12 | 15 | |||
IDRVP = 1000b, VGSx = 3V, VPVDD ≥ 7V | 12 | 16 | 20 | |||
IDRVP = 1001b, VGSx = 3V, VPVDD ≥ 7V | 15 | 20 | 25 | |||
IDRVP = 1010b, VGSx = 3V, VPVDD ≥ 7V | 18 | 24 | 30 | |||
IDRVP = 1011b, VGSx = 3V, VPVDD ≥ 7V | 21 | 28 | 35 | |||
IDRVP = 1100b, VGSx = 3V, VPVDD ≥ 7V | 23.25 | 31 | 38.75 | |||
IDRVP = 1101b, VGSx = 3V, VPVDD ≥ 7V | 26.5 | 40 | 50 | |||
IDRVP = 1110b, VGSx = 3V, VPVDD ≥ 7V | 28 | 48 | 60 | |||
IDRVP = 1111b, VGSx = 3V, VPVDD ≥ 7V | 30 | 62 | 77.5 | |||
IDRVP, H/W | Peak gate current (source) H/W Device |
IDRIVE level 1, VGSx = 3V, VPVDD ≥ 7V | 0.5 | 1 | 1.5 | mA |
IDRIVE level 2, VGSx = 3V, VPVDD ≥ 7V | 2.9 | 4 | 5.1 | |||
IDRIVE level 3, VGSx = 3V, VPVDD ≥ 7V | 6 | 8 | 10 | |||
IDRIVE level 4, VGSx = 3V, VPVDD ≥ 7V | 12 | 16 | 20 | |||
IDRIVE level 5, VGSx = 3V, VPVDD ≥ 7V | 23.25 | 31 | 38.75 | |||
IDRIVE level 6, VGSx = 3V, VPVDD ≥ 7V | 30 | 62 | 77.5 | |||
IDRVN, SPI | Peak gate current (sink) SPI Device |
IDRVN = 0000b, VGSx = 3 V, VPVDD ≥ 7 V | 0.15 | 0.5 | 0.85 | mA |
IDRVN = 0001b, VGSx = 3 V, VPVDD ≥ 7 V | 0.35 | 1 | 1.65 | |||
IDRVN = 0010b, VGSx = 3 V, VPVDD ≥ 7 V | 0.85 | 2 | 3.15 | |||
IDRVN = 0011b, VGSx = 3 V, VPVDD ≥ 7 V | 1.4 | 3 | 4.6 | |||
IDRVN = 0100b, VGSx = 3 V, VPVDD ≥ 7 V | 2.1 | 4 | 5.9 | |||
IDRVN = 0101b, VGSx = 3 V, VPVDD ≥ 7 V | 3.5 | 6 | 8.5 | |||
IDRVN = 0110b, VGSx = 3 V, VPVDD ≥ 7 V | 5 | 8 | 11 | |||
IDRVN = 0111b, VGSx = 3 V, VPVDD ≥ 7 V | 8 | 12 | 16 | |||
IDRVN = 1000b, VGSx = 3 V, VPVDD ≥ 7 V | 11.5 | 16 | 20 | |||
IDRVN = 1001b, VGSx = 3 V, VPVDD ≥ 7 V | 14.7 | 20 | 25 | |||
IDRVN = 1010b, VGSx = 3 V, VPVDD ≥ 7 V | 18 | 24 | 30 | |||
IDRVN = 1011b, VGSx = 3 V, VPVDD ≥ 7 V | 21 | 28 | 35 | |||
IDRVN = 1100b, VGSx = 3 V, VPVDD ≥ 7 V | 23.25 | 31 | 38.75 | |||
IDRVN = 1101b, VGSx = 3 V, VPVDD ≥ 7 V | 30 | 40 | 52 | |||
IDRVN = 1110b, VGSx = 3 V, VPVDD ≥ 7 V | 36 | 48 | 62 | |||
IDRVN = 1111b, VGSx = 3 V, VPVDD ≥ 7 V | 46.5 | 62 | 80 | |||
IDRVN, H/W | Peak gate current (sink) H/W Device |
IDRIVE level 1, VGSx = 3 V, VPVDD ≥ 7 V | 0.35 | 1 | 1.65 | mA |
IDRIVE level 2, VGSx = 3 V, VPVDD ≥ 7 V | 2.1 | 4 | 5.9 | |||
IDRIVE level 3, VGSx = 3 V, VPVDD ≥ 7 V | 5 | 8 | 11 | |||
IDRIVE level 4, VGSx = 3 V, VPVDD ≥ 7 V | 11.5 | 16 | 20 | |||
IDRIVE level 5, VGSx = 3 V, VPVDD ≥ 7 V | 23.25 | 31 | 38.75 | |||
IDRIVE level 6, VGSx = 3 V, VPVDD ≥ 7 V | 46.5 | 62 | 80 | |||
IHOLD | Gate pullup hold current | VGSx = 3 V, VPVDD ≥ 7 V | 5 | 16 | 30 | mA |
ISTRONG | Gate pulldown strong current | VGSx = 3 V, VPVDD ≥ 7 V, 0.5 ≤ IDRVP ≤ 12 mA |
30 | 62 | 100 | mA |
VGSx = 3 V, VPVDD ≥ 7 V, 16 ≤ IDRVP ≤ 62 mA |
45 | 128 | 205 | mA | ||
RPDSA_LS | Low-side semi-active pulldown | GLx to SLx, VGSx = 3 V | 1.8 | kΩ | ||
GLx to SLx, VGSx = 1 V | 5 | kΩ | ||||
RPD_HS | High-side passive pulldown resistor | GHx to SHx | 150 | kΩ | ||
RPD_LS | Low-side passive pulldown resistor | GLx to SLx | 150 | kΩ | ||
ISHx | Switch-node sense leakage current | Into SHx, SHx = DRAIN ≤ 37 V GHx – SHx = 0 V, nSLEEP = 0 V |
–5 | 0 | 25 | µA |
Into SHx, SHx = DRAIN ≤ 37 V GHx – SHx = 0 V, nSLEEP = 5 V |
–150 | –100 | –40 | µA | ||
GATE DRIVER TIMINGS (GHx, GLx) | ||||||
tPDR_LS | Low-side rising propagation delay | Input to GLx rising | 300 | 850 | ns | |
tPDF_LS | Low-side falling propagation delay | Input to GLx falling | 300 | 600 | ns | |
tPDR_HS | High-side rising propagation delay | Input to GHx rising | 300 | 600 | ns | |
tPDF_HS | High-side falling propagation delay | Input to GHx falling | 300 | 600 | ns | |
tDEAD | Internal handshake dead-time | VGSx_L/VGSx_H falling 10% to VGSx_H/VGSx_L rising 10% | 350 | ns | ||
tDEAD_D, SPI | Insertable digital dead-time SPI Device |
VGS_TDEAD = 000b, Handshake only | 0 | ns | ||
VGS_TDEAD = 001b | 150 | 250 | 350 | |||
VGS_TDEAD = 010b | 400 | 500 | 600 | |||
VGS_TDEAD = 011b | 600 | 750 | 900 | |||
VGS_TDEAD = 100b | 800 | 1000 | 1200 | |||
VGS_TDEAD = 101b | 1600 | 2000 | 2400 | |||
VGS_TDEAD = 110b | 3400 | 4000 | 4600 | |||
VGS_TDEAD = 111b | 7200 | 8000 | 8800 | |||
tDEAD_D, H/W | Insertable digital dead-time H/W Device |
Handshake only | 0 | ns | ||
CURRENT SHUNT AMPLIFIERS (AREF, SN, SO, SP) | ||||||
VCOM | Common mode input range | –2 | 2 | V | ||
GCSA, SPI | Sense amplifier gain SPI device |
CSA_GAIN = 00b | 9.9 | 10.15 | 10.4 | V/V |
CSA_GAIN = 01b | 19.5 | 20 | 20.5 | |||
CSA_GAIN = 10b | 39 | 40 | 41 | |||
CSA_GAIN = 11b | 78 | 80 | 82 | |||
GCSA, H/W | Sense amplifier gain H/W device |
GAIN quad-level 1 | 9.9 | 10.15 | 10.4 | V/V |
GAIN quad-level 2 | 19.5 | 20 | 20.5 | |||
GAIN quad-level 3 | 39 | 40 | 41 | |||
GAIN quad-level 4 | 78 | 80 | 82 | |||
tSET | Sense amplifier settling time to ±1% | VSO_
STEP = 1.5 V, GCSA = 10 V/V CSO = 60 pF |
2.2 | µs | ||
VSO_
STEP = 1.5 V, GCSA = 20 V/V CSO = 60 pF |
2.2 | |||||
VSO_
STEP = 1.5 V, GCSA = 40 V/V CSO = 60 pF |
2.2 | |||||
VSO_
STEP = 1.5 V, GCSA = 80 V/V CSO = 60 pF |
3 | |||||
tBLK, SPI | Sense amplifier output blanking time SPI Device |
CSA_BLK = 000b, % of tDRIVE period | 0 | % | ||
CSA_BLK = 001b, % of tDRIVE period | 25 | |||||
CSA_BLK = 010b, % of tDRIVE period | 37.5 | |||||
CSA_BLK = 011b, % of tDRIVE period | 50 | |||||
CSA_BLK = 100b, % of tDRIVE period | 62.5 | |||||
CSA_BLK = 101b, % of tDRIVE period | 75 | |||||
CSA_BLK = 110b, % of tDRIVE period | 87.5 | |||||
CSA_BLK = 111b, % of tDRIVE period | 100 | |||||
tBLK, H/W | Sense amplifier output blanking time H/W Device |
0 | ns | |||
tSLEW | Output slew rate | CSO = 60 pF | 2.5 | V/µs | ||
VBIAS, SPI | Output voltage bias SPI Device |
VSPx = VSNx = 0 V, CSA_DIV = 0b | VAREF / 2 | V | ||
VSPx = VSNx = 0 V, CSA_DIV = 1b | VAREF / 8 | |||||
VBIAS, H/W | Output voltage bias H/W Device |
VAREF / 2 | V | |||
VLINEAR | Linear output voltage range | VAREF = 3.3 V = 5 V | 0.25 | VAREF – 0.25 | V | |
VOFF | Input offset voltage | VSPx = VSNx = 0 V, TJ = 25℃ | –1.5 | 1.5 | mV | |
VOFF_D | Input offset voltage drift | VSPx = VSNx = 0 V | ±10 | ±25 | µV/℃ | |
IBIAS | Input bias current | VSPx = VSNx = 0 V, into pin | 100 | µA | ||
IBIAS_OFF | Input bias current offset | ISPx – ISNx | –1 | 1 | µA | |
IAREF | AREF input current | VVREF = 3.3 V = 5 V | 1 | 1.8 | mA | |
CMRR | Common mode rejection ratio | DC, –40 ≤ TJ ≤ 125°C | 72 | 90 | dB | |
DC, –40 ≤ TJ ≤ 150°C | 69 | 90 | ||||
20kHz | 80 | |||||
PSRR | Power supply rejection ratio | PVDD to SOx, DC | 100 | dB | ||
PVDD to SOx, 20kHz | 90 | |||||
PVDD to SOx, 400kHz | 70 | |||||
PROTECTION CIRCUITS | ||||||
VPVDD_UV | PVDD undervoltage threshold | VPVDD rising | 4.325 | 4.625 | 4.9 | V |
VPVDD falling | 4.25 | 4.525 | 4.8 | |||
VPVDD_UV_HYS | PVDD undervoltage hysteresis | Rising to falling threshold | 100 | mV | ||
tPVDD_UV_DG | PVDD undervoltage deglitch time | 8 | 10 | 12.75 | µs | |
VPVDD_OV | PVDD overvoltage threshold | VPVDD rising, PVDD_OV_LVL = 0b | 21 | 22.5 | 24 | V |
VPVDD falling, PVDD_OV_LVL = 0b | 20 | 21.5 | 23 | |||
VPVDD rising, PVDD_OV_LVL = 1b | 27 | 28.5 | 30 | |||
VPVDD falling, PVDD_OV_LVL = 1b | 26 | 27.5 | 29 | |||
VPVDD_OV_HYS | PVDD overvoltage hysteresis | Rising to falling threshold | 1 | V | ||
tPVDD_OV_DG | PVDD overvoltage deglitch time | PVDD_OV_DG = 00b | 0.75 | 1 | 1.5 | µs |
PVDD_OV_DG = 01b | 1.5 | 2 | 2.5 | |||
PVDD_OV_DG = 10b | 3.25 | 4 | 4.75 | |||
PVDD_OV_DG = 11b | 7 | 8 | 9 | |||
VDVDD_POR | DVDD supply POR threshold | DVDD falling | 2.5 | 2.7 | 2.9 | V |
DVDD rising | 2.6 | 2.8 | 3 | |||
VDVDD_POR_HYS | DVDD POR hysteresis | Rising to falling threshold | 100 | mV | ||
tDVDD_POR_DG | DVDD POR deglitch time | 5 | 8 | 12.75 | µs | |
VCP_UV, SPI | Charge pump undervoltage threshold SPI Device |
VVCP - VPVDD, falling, VCP_UV = 0b | 2 | 2.5 | 3 | V |
VVCP - VPVDD, falling, VCP_UV = 1b | 4 | 5 | 6 | |||
VCP_UV, H/W | Charge pump undervoltage threshold H/W Device |
2 | 2.5 | 3 | V | |
tCP_UV_DG | Charge pump undervoltage deglitch time | 8 | 10 | 12.75 | µs | |
VGS_CLP | High-side driver VGS protection clamp | 12.5 | 15 | 17 | V | |
VGS_LVL | Gate voltage monitor threshold | VGH/Lx – VSH/Lx, VGS_LVL = 0b | 1.1 | 1.4 | 1.75 | V |
VGH/Lx – VSH/Lx, VGS_LVL = 1b | 0.8 | 1 | 1.2 | V | ||
tGS_FLT_DG | VGS fault monitor deglitch time | 1.5 | 2 | 2.75 | µs | |
tGS_HS_DG | VGS handshake monitor deglitch time | 210 | ns | |||
tDRIVE, SPI | VGS and VDS monitor blanking time SPI Device |
VGS_TDRV = 00b | 80 | 96 | 120 | µs |
VGS_TDRV = 01b | 1.5 | 2 | 2.5 | |||
VGS_TDRV = 10b | 3.25 | 4 | 4.75 | |||
VGS_TDRV = 11b | 7.5 | 8 | 9 | |||
tDRIVE, H/W | VGS and VDS monitor blanking time H/W Device |
3.25 | 4 | 4.75 | µs | |
VDS_LVL, SPI | VDS overcurrent protection threshold SPI Device |
VDS_LVL = 0000b | 0.04 | 0.06 | 0.08 | V |
VDS_LVL = 0001b | 0.06 | 0.08 | 0.10 | |||
VDS_LVL = 0010b | 0.08 | 0.10 | 0.12 | |||
VDS_LVL = 0011b | 0.10 | 0.12 | 0.14 | |||
VDS_LVL = 0100b | 0.12 | 0.14 | 0.16 | |||
VDS_LVL = 0101b | 0.14 | 0.16 | 0.18 | |||
VDS_LVL = 0110b | 0.16 | 0.18 | 0.20 | |||
VDS_LVL = 0111b | 0.18 | 0.2 | 0.22 | |||
VDS_LVL = 1000b | 0.27 | 0.3 | 0.33 | |||
VDS_LVL = 1001b | 0.36 | 0.4 | 0.44 | |||
VDS_LVL = 1010b | 0.45 | 0.5 | 0.55 | |||
VDS_LVL = 1011b | 0.54 | 0.6 | 0.66 | |||
VDS_LVL = 1100b | 0.63 | 0.7 | 0.77 | |||
VDS_LVL = 1101b | 0.9 | 1 | 1.1 | |||
VDS_LVL = 1110b | 1.26 | 1.4 | 1.54 | |||
VDS_LVL = 1111b | 1.8 | 2 | 2.2 | |||
VDS_LVL, H/W | VDS overcurrent protection threshold H/W Device |
VDS six-level input 1 | 0.04 | 0.06 | 0.08 | V |
VDS six-level input 2 | 0.08 | 0.10 | 0.12 | |||
VDS six-level input 3 | 0.18 | 0.2 | 0.22 | |||
VDS six-level input 4 | 0.45 | 0.5 | 0.55 | |||
VDS six-level input 5 | 0.9 | 1 | 1.1 | |||
VDS six-level input 6 | Disabled | |||||
tDS_DG, SPI | VDS overcurrent protection deglitch time SPI Device |
VDS_DG = 00b | 0.75 | 1 | 1.5 | µs |
VDS_DG = 01b | 1.5 | 2 | 2.5 | |||
VDS_DG = 10b | 3.25 | 4 | 4.75 | |||
VDS_DG = 11b | 7.5 | 8 | 9 | |||
tDS_DG, H/W | VDS overcurrent protection deglitch time H/W Device |
3.25 | 4 | 4.75 | µs | |
IOLD | Offline diagnostic current source | Pull up current | 3 | mA | ||
Pull down current | 3 | |||||
ROLD | Offline open load resistance detection threshold | VDS_LVL = 1.4 V, VPVDD ≤ 18 V | 22 | 50 | kΩ | |
VDS_LVL = 1.4 V, VPVDD ≤ 37 V | 22 | 100 | kΩ | |||
VDS_LVL = 2 V, VPVDD ≤ 18 V | 10 | 25 | kΩ | |||
VDS_LVL = 2 V, VPVDD ≤ 37 V | 10 | 50 | kΩ | |||
TOTW | Thermal warning temperature | TJ rising | 130 | 150 | 170 | °C |
THYS | Thermal warning hysteresis | 20 | °C | |||
TOTSD | Thermal shutdown temperature | TJ rising | 150 | 170 | 190 | °C |
THYS | Thermal shutdown hysteresis | 20 | °C |