SLLSFA7A July 2020 – April 2021 DRV8706-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Table 7-13 lists the memory-mapped registers for the STATUS registers. All register offset addresses not listed in Table 7-13 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
0h | IC_STAT_1 | IC status register 1 | Go |
1h | VGS_VDS_STAT | VGS and VDS status register | Go |
2h | IC_STAT_2 | IC status register 2 | Go |
3h | RSVD_STAT | Reserved | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-14 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Reset or Default Value | ||
-n | Value after reset or the default value |
IC_STAT_1 is shown in Figure 7-28 and described in Table 7-15.
Return to Summary Table.
Status register with the primary IC fault bits
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPI_OK | POR | FAULT | WARN | DS_GS | UV | OV | OT |
R-1b | R-1b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SPI_OK | R | 1b | No SPI fault is detected.
0b = One or multiple of SPI_CLK_FLT or SPI_ADR_FLT in the past frames. 1b = No SPI fault is detected |
6 | POR | R | 1b | Indicated power-on-reset condition.
0b = No power-on-reset condition is detected. 1b = Power-on reset condition is detected. |
5 | FAULT | R | 0b | Fault indicator. Mirrors nFAULT pin. |
4 | WARN | R | 0b | Warning indicator. |
3 | DS_GS | R | 0b | Logic OR of VDS and VGS indicators. |
2 | UV | R | 0b | Undervoltage indicator. |
1 | OV | R | 0b | Overvoltage indicator. |
0 | OT | R | 0b | Logic OR of OTW and OTSD indicators. |
VGS_VDS_STAT is shown in Figure 7-29 and described in Table 7-16.
Return to Summary Table.
Status register with the VGS and VDS fault bits
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VGS_H1 | VGS_L1 | VGS_H2 | VGS_L2 | VDS_H1 | VDS_L1 | VDS_H2 | VDS_L2 |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | VGS_H1 | R | 0b | Indicates VGS gate fault on the high-side 1 MOSFET. |
6 | VGS_L1 | R | 0b | Indicates VGS gate fault on the low-side 1 MOSFET. |
5 | VGS_H2 | R | 0b | Indicates VGS gate fault on the high-side 2 MOSFET. |
4 | VGS_L2 | R | 0b | Indicates VGS gate fault on the low-side 2 MOSFET. |
3 | VDS_H1 | R | 0b | Indicates VDS overcurrent fault on the high-side 1 MOSFET. |
2 | VDS_L1 | R | 0b | Indicates VDS overcurrent fault on the low-side 1 MOSFET. |
1 | VDS_H2 | R | 0b | Indicates VDS overcurrent fault on the high-side 2 MOSFET. |
0 | VDS_L2 | R | 0b | Indicates VDS overcurrent fault on the low-side 2 MOSFET. |
IC_STAT_2 is shown in Figure 7-30 and described in Table 7-17.
Return to Summary Table.
Status register with IC undervoltage, overvoltage, and SPI fault bits
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PVDD_UV | PVDD_OV | VCP_UV | OTW | OTSD | RESERVED | SCLK_FLT | ADDR_FLT |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PVDD_UV | R | 0b | indicates undervoltage fault on PVDD pin. |
6 | PVDD_OV | R | 0b | Indicates overvoltage fault on PVDD pin. |
5 | VCP_UV | R | 0b | Indicates undervoltage fault on VCP pin. |
4 | OTW | R | 0b | Indicates overtemperature warning. |
3 | OTSD | R | 0b | Indicates overtemperature shutdown. |
2 | RESERVED | R | 0b | Reserved. |
1 | SCLK_FLT | R | 0b | Indicates SPI clock (frame) fault. |
0 | ADDR_FLT | R | 0b | Indicates SPI address fault. |
RSVD_STAT is shown in Figure 7-31 and described in Table 7-18.
Return to Summary Table.
Reserved status register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0b | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | RESERVED | R | 0b | Reserved |