SLVSFL8 July   2021 DRV8770

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 Gate Drive Timings
          1. 7.3.1.1.1 Propagation Delay
          2. 7.3.1.1.2 Deadtime and Cross-Conduction Prevention
        2. 7.3.1.2 Mode (Inverting and non-inverting INLx)
      2. 7.3.2 Pin Diagrams
      3. 7.3.3 Gate Driver Protective Circuits
        1. 7.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
        2. 7.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Example
    2. 10.2 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The DRV8770 device provides two half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The integrated bootstrap diode and external capacitor generate the correct gate drive voltages for the high-side MOSFETs while the GVDD drives the gates of the low-side MOSFETs. The gate drive architecture supports gate drive currents up to 750-mA source and 1.5-A sink.

The high voltage tolerance of the gate drive pins improves system robustness. The SHx phase pins can tolerate significant negative voltage transients, while the high-side gate driver supply can support higher positive voltage transients (115-V absolute maximum) on the BSTx and GHx pins. Small propagation delay and delay matching specifications minimize the dead-time requirement which further improves efficiency. Undervoltage protection is provided for both low and high side through GVDD and BST undervoltage lockout.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
DRV8770PW TSSOP (20) 6.40 mm × 4.40 mm
DRV8770RGE VQFN (24) 4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
Simplified Schematic for DRV8770