SLVSFL8 July   2021 DRV8770

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 Gate Drive Timings
          1. 7.3.1.1.1 Propagation Delay
          2. 7.3.1.1.2 Deadtime and Cross-Conduction Prevention
        2. 7.3.1.2 Mode (Inverting and non-inverting INLx)
      2. 7.3.2 Pin Diagrams
      3. 7.3.3 Gate Driver Protective Circuits
        1. 7.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
        2. 7.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Example
    2. 10.2 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 DRV8770 RGE Package24-Pin VQFN With Exposed Thermal PadTop View
Table 5-1 Pin Functions—24-Pin DRV8770 Device
PIN TYPE(1) DESCRIPTION
NAME NO.
BSTA 20 O Bootstrap output pin. Connect capacitor between BSTA and SHA
BSTB 17 O Bootstrap output pin. Connect capacitor between BSTB and SHB
DT 21 I Deadtime input pin. Connect resistor to ground for variable deadtime, fixed deadtime when left it floating
GHA 19 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 11 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND 6 PWR Device ground.
GVDD 4 PWR Gate driver power supply input. Connect a X5R or X7R, GVDD-rated ceramic and greater then or equal to 10-uF local capacitance between the GVDD and GND pins.
INHA 22 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 23 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 1 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 2 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 5 I Mode Input controls polarity of GLx compared to INLx inputs.
Mode pin floating: GLx output polarity same(Non-Inverted) as INLx input
Mode pin to GVDD: GLx output polarity inverted compared to INLx input
NC 7, 8 NC No internal connection. This pin can be left floating or connected to system ground.
RSVD1, RSVD2, RSVD3, RSVD5, RSVD6 3, 9, 13, 14, 24 I TI reserved pin. Leave pin floating.
RSVD4 12 I TI reserved pin. Connect to GND
SHA 18 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 15 I High-side source sense input. Connect to the high-side power MOSFET source.
(1) PWR = power, I = input, O = output, NC = no connection
Figure 5-2 DRV8770 PW Package20-Pin TSSOPTop View
Table 5-2 Pin Functions—20-Pin DRV8770 Device
PIN TYPE(1) DESCRIPTION
NAME NO.
BSTA 20 O Bootstrap output pin. Connect capacitor between BSTA and SHA
BSTB 17 O Bootstrap output pin. Connect capacitor between BSTB and SHB
GHA 19 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 11 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND 8 PWR Device ground.
GVDD 7 PWR Gate driver power supply input. Connect a X5R or X7R, GVDD-rated ceramic and greater then or equal to 10-uF local capacitance between the GVDD and GND pins.
INHA 1 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 2 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 4 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 5 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
RSVD1, RSVD2, RSVD3, RSVD5, RSVD6 3, 6, 9, 13, 14 I TI reserved pin. Leave pin floating.
RSVD4 12 I TI reserved pin. Connect to GND
SHA 18 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 15 I High-side source sense input. Connect to the high-side power MOSFET source.
(1) PWR = power, I = input, O = output, NC = no connection