SLVSFL8 July   2021 DRV8770

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 Gate Drive Timings
          1. 7.3.1.1.1 Propagation Delay
          2. 7.3.1.1.2 Deadtime and Cross-Conduction Prevention
        2. 7.3.1.2 Mode (Inverting and non-inverting INLx)
      2. 7.3.2 Pin Diagrams
      3. 7.3.3 Gate Driver Protective Circuits
        1. 7.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
        2. 7.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Example
    2. 10.2 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.1.1.2 Deadtime and Cross-Conduction Prevention

In the DRV8770, high- and low-side inputs operate independently, with an exception to prevent cross conduction when high and low side are turned ON at same time. The DRV8770 turns OFF high- and low- side output to prevent shoot through when high- and low-side inputs are logic high at same time.

The DRV8770 also provides deadtime insertion to prevents both external MOSFETs of each power-stage from switching on at the same time. In devices with DT pin (QFN package device), deadtime can be linearily adjusted between 200 ns to 2000 ns by connecting resistor between DT and ground. When DT pin is connected to ground, fixed deadtime of 200 ns (typical value) is inserted. The value of resistor can be caculated using Equation 1.

Equation 1. GUID-20210601-CA0I-PMCR-XFTJ-9GTGBMPVJJZR-low.png

In device without DT pin (TSSOP package device), fixed deadtime of 200 ns (Typical value) is inserted to prevent high and low side gate output turning on at same time.

GUID-F1F8F7D0-544C-4DFE-AF93-03A2015BBBA7-low.gif Figure 7-2 Cross Conduction Prevention and Deadtime Insertion