The DRV8884 device is a stepper motor driver for industrial equipment applications. The device has two N-channel power MOSFET H-bridge drivers, a microstepping indexer, and integrated current sense. The DRV8884 is capable of driving up to 1.0-A full scale or 0.7-A rms output current (depending on proper PCB ground plane for thermal dissipation and at 24 V and TA = 25°C).
The DRV8884 integrated current sense functionality eliminates the need for two external sense resistors.
The STEP/DIR pins provide a simple control interface. The device can be configured in full-step up to 1/16 step modes. A low-power sleep mode is provided for very-low quiescent current standby using a dedicated nSLEEP pin.
Internal protection functions are provided for undervoltage, charge pump faults, overcurrent, short circuits, and overtemperature. Fault conditions are indicated by an nFAULT pin.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8884 | HTSSOP (24) | 7.80 mm × 4.40 mm |
WQFN (28) | 5.50 mm × 3.5 mm |
Changes from D Revision (November 2018) to E Revision
Changes from C Revision (July 2018) to D Revision
Changes from B Revision (April 2016) to C Revision
Changes from A Revision (March 2016) to B Revision
Changes from * Revision (January 2016) to A Revision
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
HTSSOP | WQFN | |||
AOUT1 | 5 | 3 | O | Winding A output. Connect to stepper motor winding. |
AOUT2 | 7 | 5 | ||
AVDD | 13 | 12 | PWR | Internal regulator. Bypass to GND with a X5R or X7R, 0.47-μF, 6.3-V ceramic capacitor. |
BOUT1 | 10 | 8 | O | Winding B output. Connect to stepper motor winding. |
BOUT2 | 8 | 6 | ||
CPH | 2 | 28 | PWR | Charge pump switching node. Connect a X5R or X7R, 0.022-μF, VM-rated ceramic capacitor from CPH to CPL. |
CPL | 1 | 27 | ||
DECAY | 24 | 25 | I | Decay-mode setting. Sets the decay mode (see the Decay Modes section). Decay mode can be adjusted during operation. |
DIR | 20 | 21 | I | Direction input. Logic level sets the direction of stepping; internal pulldown resistor. |
DVDD | 14 | 13 | PWR | Internal regulator. Bypass to GND with a X5R or X7R, 0.47-μF, 6.3-V ceramic capacitor. |
ENABLE | 18 | 19 | I | Enable driver input. Logic high to enable device outputs; logic low to disable; internal pulldown resistor. |
GND | 12 | 10 | PWR | Device ground. Connect to system ground. |
M0 | 21 | 22 | I | Microstepping mode-setting. Sets the step mode; tri-level pins; sets the step mode; internal pulldown resistor. |
M1 | 22 | 23 | ||
NC | — | 11 | — | No connect. No internal connection |
14 | ||||
15 | ||||
26 | ||||
PGND | 6 | 4 | PWR | Power ground. Connect to system ground. |
9 | 7 | |||
RREF | 16 | 17 | I | Current-limit analog input. Connect a resistor to ground to set full-scale regulation current. |
STEP | 19 | 20 | I | Step input. A rising edge causes the indexer to advance one step; internal pulldown resistor. |
TRQ | 23 | 24 | I | Current-scaling control. Scales the output current; tri-level pin. |
VCP | 3 | 1 | PWR | Charge pump output. Connect a X5R or X7R, 0.22-μF, 16-V ceramic capacitor to VM. |
VM | 4 | 2 | PWR | Power supply. Connect to motor supply voltage and bypass to GND with two 0.01-μF ceramic capacitors (one for each pin) plus a bulk capacitor rated for VM. |
11 | 9 | |||
nFAULT | 15 | 16 | OD | Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor. |
nSLEEP | 17 | 18 | I | Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor. |
MIN | MAX | UNIT | |
---|---|---|---|
Power supply voltage (VM) | –0.3 | 40 | V |
Power supply voltage ramp rate (VM) | 0 | 2 | V/µs |
Charge pump voltage (VCP, CPH) | –0.3 | VM + 7 | V |
Charge pump negative switching pin (CPL) | –0.3 | VM | V |
Internal regulator voltage (DVDD) | –0.3 | 3.8 | V |
Internal regulator current output (DVDD) | 0 | 1 | mA |
Internal regulator voltage (AVDD) | –0.3 | 5.7 | V |
Control pin voltage (STEP, DIR, ENABLE, nFAULT, M0, M1, DECAY, TRQ, nSLEEP) | –0.3 | 5.7 | V |
Open drain output current (nFAULT) | 0 | 10 | mA |
Current limit input pin voltage (RREF) | –0.3 | 6.0 | V |
Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2) | –0.7 | VM + 0.7 | V |
Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2) | 1.7 | A | |
Operating junction temperature, TJ | –40 | 150 | °C |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VM | Power supply voltage | 8 | 37 | V |
VCC | Logic level input voltage | 0 | 5.3 | V |
ƒPWM | Applied STEP signal (STEP) | 0 | 100 (1) | kHz |
IDVDD | DVDD external load current | 0 | 1 (2) | mA |
IFS | Motor full scale current | 0 | 1.0 | A |
Irms | Motor rms current | 0 | 0.7 | A |
TA | Operating ambient temperature | –40 | 125 | °C |
THERMAL METRIC (1) | DRV8884 | UNIT | ||
---|---|---|---|---|
PWP (HTSSOP) | RHR (WQFN) | |||
24 PINS | 28 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 36.1 | 33.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 18.3 | 23.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 15.8 | 12.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.4 | 0.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 15.7 | 12.6 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.1 | 3.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLIES (VM, DVDD, AVDD) | ||||||
VVM | VM operating voltage | 8 | 37 | V | ||
IVM | VM operating supply current | VM ≈ 8 to 35 V, ENABLE = 1, nSLEEP = 1, No motor load | 5 | 8 | mA | |
IVMQ | VM sleep mode supply current | nSLEEP = 0; TA = 25°C | 20 | μA | ||
nSLEEP = 0; TA = 125°C (1) | 40 | |||||
tSLEEP | Sleep time | nSLEEP = 0 to sleep-mode | 50 | 200 | μs | |
tWAKE | Wake-up time | nSLEEP = 1 to output transition | 0.85 | 1.5 | ms | |
tON | Turn-on time | VM > UVLO to output transition | 0.85 | 1.5 | ms | |
VDVDD | Internal regulator voltage | 0- to 1-mA external load | 2.9 | 3.3 | 3.6 | V |
VAVDD | Internal regulator voltage | No external load | 4.5 | 5.0 | 5.5 | V |
CHARGE PUMP (VCP, CPH, CPL) | ||||||
VVCP | VCP operating voltage | VM > 8 V | VM + 5.5 | V | ||
LOGIC-LEVEL INPUTS (STEP, DIR, ENABLE, nSLEEP, M1) | ||||||
VIL | Input logic low voltage | 0 | 0.8 | V | ||
VIH | Input logic high voltage | 1.6 | 5.3 | V | ||
VHYS | Input logic hysteresis | 100 | mV | |||
IIL | Input logic low current | VIN = 0 V | –1 | 1 | μA | |
IIH | Input logic high current | VIN = 5.0 V | 100 | μA | ||
RPD | Pulldown resistance | To GND | 100 | kΩ | ||
tPD | Propagation delay | STEP to current change | 1.2 | μs | ||
TRI-LEVEL INPUT (M0, TRQ) | ||||||
VIL | Tri-level input logic low voltage | 0 | 0.65 | V | ||
VIZ | Tri-level input Hi-Z voltage | 1.1 | V | |||
VIH | Tri-level input logic high voltage | 1.5 | 5.3 | V | ||
IIL | Tri-level input logic low current | VIN = 0 V | –80 | μA | ||
IIZ | Tri-level input Hi-Z current | VIN = 1.3 V | –5 | 5 | μA | |
IIH | Tri-level input logic high current | VIN = 5.0 V | 155 | μA | ||
RPD | Tri-level pulldown resistance | To GND | 18 | 32 | 50 | kΩ |
RPU | Tri-level pullup resistance | To DVDD | 30 | 60 | 90 | kΩ |
QUAD-LEVEL INPUT (DECAY) | ||||||
VI1 | Quad-level input voltage 1 | 5% resistor 5 kΩ to GND | 0.07 | 0.11 | 0.13 | V |
VI2 | Quad-level input voltage 2 | 5% resistor 15 kΩ to GND | 0.24 | 0.32 | 0.40 | V |
VI3 | Quad-level input voltage 3 | 5% resistor 45 kΩ to GND | 0.71 | 0.97 | 1.20 | V |
VI4 | Quad-level input voltage 4 | 5% resistor 135 kΩ to GND | 2.12 | 2.90 | 3.76 | V |
IO | Output current | To GND | 14 | 22 | 30 | μA |
CONTROL OUTPUTS (nFAULT) | ||||||
VOL | Output logic low voltage | IO = 1 mA, RPULLUP = 4.7 kΩ | 0.5 | V | ||
IOH | Output logic high leakage | VO = 5.0 V, RPULLUP = 4.7 kΩ | –1 | +1 | μA | |
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2) | ||||||
RDS(ON) | High-side FET on resistance | VM = 24 V, I = 1 A, TA = 25°C | 716 | 798 | mΩ | |
RDS(ON) | Low-side FET on resistance | VM = 24 V, I = 1 A, TA = 25°C | 684 | 749 | mΩ | |
tRISE(2) | Output rise time | 100 | ns | |||
tFALL(2) | Output fall time | 100 | ns | |||
tDEAD(2) | Output dead time | 200 | ns | |||
Vd(2) | Body diode forward voltage | IOUT = 0.5 A | 0.7 | 1.0 | V | |
PWM CURRENT CONTROL (RREF) | ||||||
ARREF | RREF transimpedance gain | 28.1 | 30 | 31.9 | kAΩ | |
VRREF | RREF voltage | RREF = 27 to 132 kΩ | 1.18 | 1.232 | 1.28 | V |
tOFF | PWM off-time | 20 | μs | |||
CRREF | Equivalent capacitance on RREF | 10 | pF | |||
tBLANK | PWM blanking time | IRREF = 1.0 A, 63% to 100% current setting | 1.5 | µs | ||
IRREF = 1.0 A, 0% to 63% current setting | 1.0 | |||||
ΔITRIP | Current trip accuracy | IRREF = 1.0 A, 10% to 20% current setting, 1% reference resistor | –25% | 25% | ||
IRREF = 1.0 A, 20% to 63% current setting, 1% reference resistor | –12.5% | 12.5% | ||||
IRREF = 1.0 A, 71% to 100% current setting, 1% reference resistor | –6.25% | 6.25% | ||||
PROTECTION CIRCUITS | ||||||
VUVLO | VM UVLO | VM falling; UVLO report | 7.8 | V | ||
VM rising; UVLO recovery | 8.0 | |||||
VUVLO,HYS | Undervoltage hysteresis | Rising to falling threshold | 100 | mV | ||
VCPUV | Charge pump undervoltage | VCP falling; CPUV report | VM + 2.0 | V | ||
IOCP | Overcurrent protection trip level | Current through any FET | 1.7 | A | ||
tOCP | Overcurrent deglitch time | 1.3 | 1.9 | 2.8 | μs | |
tRETRY | Overcurrent retry time | 1 | 1.6 | ms | ||
TTSD(2) | Thermal shutdown temperature | Die temperature TJ | 150 | °C | ||
THYS(2) | Thermal shutdown hysteresis | Die temperature TJ | 20 | °C |