SLOSE71 April   2020  – December 2020 DRV8955

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Configuration Options and Bridge Control
      2. 7.3.2 Current Regulation
      3. 7.3.3 Charge Pump
      4. 7.3.4 Linear Voltage Regulators
      5. 7.3.5 Logic and Quad-Level Pin Diagrams
        1. 7.3.5.1 nFAULT Pin
      6. 7.3.6 Protection Circuits
        1. 7.3.6.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.6.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.6.3 Overcurrent Protection (OCP)
        4. 7.3.6.4 Thermal Shutdown (OTSD)
        5.       Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Operating Mode (nSLEEP = 1)
      3. 7.4.3 nSLEEP Reset Pulse
      4.      Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Regulation
        2. 8.2.2.2 Power Dissipation and Thermal Calculation
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES (VM, DVDD)
IVMVM operating supply currentnSLEEP = 1, No load56.5mA
IVMQVM sleep mode supply currentnSLEEP = 024μA
tSLEEPSleep timenSLEEP = 0 to sleep-mode120μs
tRESETnSLEEP reset pulsenSLEEP low to clear fault2040μs
tWAKEWake-up timenSLEEP = 1 to output transition0.81.2ms
tONTurn-on timeVM > UVLO to output transition0.81.2ms
VDVDDInternal regulator voltageNo external load, 6 V < VVM < 48 V4.7555.25V
No external load, VVM = 4.5 V

4.2

4.35

V

CHARGE PUMP (VCP, CPH, CPL)
VVCPVCP operating voltage6 V < VVM < 48 VVVM + 5V
f(VCP)Charge pump switching frequencyVVM > UVLO; nSLEEP = 1360kHz
LOGIC-LEVEL INPUTS (IN1, IN2, IN3, IN4, EN1, EN2, EN3, EN4, nSLEEP)
VILInput logic-low voltage00.6V
VIHInput logic-high voltage1.55.5V
VHYSInput logic hysteresis150mV
IILInput logic-low currentVIN = 0 V–11μA
IIHInput logic-high currentVIN = 5 V100μA

t1

ENx high to OUTx high delay

INx = 1

5

μs

t2

ENx low to OUTx low delayINx = 1

5

μs

t3

ENx high to OUTx low delayINx = 0

5

μs

t4

ENx low to OUTx high delayINx = 0

5

μs

t5

INx high to OUTx high delay

800

ns

t6

INx low to OUTx low delay

800

ns

QUAD-LEVEL INPUTS (MODE, TOFF)
VI1Input logic-low voltageTied to GND00.6V
VI2330kΩ ± 5% to GND11.251.4V
VI3Input Hi-Z voltageHi-Z (>500kΩ to GND)1.822.2V
VI4Input logic-high voltageTied to DVDD2.75.5V
IOOutput pull-up current10μA
CONTROL OUTPUTS (nFAULT)
VOLOutput logic-low voltageIO = 5 mA0.5V
IOHOutput logic-high leakage–11μA
MOTOR DRIVER OUTPUTS (OUT1, OUT2, OUT3, OUT4)
RDS(ONH)High-side FET on resistance (MODE = 0 or 330k to GND)TJ = 25 °C, IO = -1 A165200mΩ
TJ = 125 °C, IO = -1 A250300mΩ
TJ = 150 °C, IO = -1 A280350mΩ
RDS(ONL)Low-side FET on resistance (MODE = 0 or 330k to GND)TJ = 25 °C, IO = 1 A165200mΩ
TJ = 125 °C, IO = 1 A250300mΩ
TJ = 150 °C, IO = 1 A280350mΩ
RDS(ONH)High-side FET on resistance (MODE = 1)TJ = 25 °C, IO = -1 A

80

100

mΩ
TJ = 125 °C, IO = -1 A

125

150

mΩ
TJ = 150 °C, IO = -1 A

140

175

mΩ
RDS(ONL)Low-side FET on resistance (MODE = 1)TJ = 25 °C, IO = 1 A

80

100

mΩ
TJ = 125 °C, IO = 1 A

125

150

mΩ
TJ = 150 °C, IO = 1 A

140

175

mΩ
RDS(ONH)High-side FET on resistance (MODE = Hi-Z)TJ = 25 °C, IO = -1 A

40

50

mΩ
TJ = 125 °C, IO = -1 A

60

75

mΩ
TJ = 150 °C, IO = -1 A

70

90

mΩ
RDS(ONL)Low-side FET on resistance (MODE = Hi-Z)TJ = 25 °C, IO = 1 A

40

50

mΩ
TJ = 125 °C, IO = 1 A

60

75

mΩ
TJ = 150 °C, IO = 1 A

70

90

mΩ

tRF

Output rise/fall time

VM = 24V

100

ns

CURRENT REGULATION (VREF)
KVTransimpedance gain

VREF = 3.3V, MODE = 0 or 330k to GND

1.2541.321.386V/A
VREF = 3.3V, MODE = 1

0.627

0.66

0.693

V/A
VREF = 3.3V, MODE = Hi-Z

0.313

0.33

0.347

V/A

IVREF

VREF leakage current

VREF = 3.3V

8.25

μA
tOFFPWM off-timeTOFF = 07μs
TOFF = 116
TOFF = Hi-Z24
TOFF = 330 kΩ to GND32
ΔITRIPCurrent trip accuracy10% to 20% of ITRIP setting

-12

12

%

20% to 40% of ITRIP setting

-6

6

40% to 100% ITRIP setting

-4

4

PROTECTION CIRCUITS
VUVLOVM UVLO lockoutVM falling, UVLO falling4.14.254.35V
VM rising, UVLO rising4.24.354.45
VUVLO,HYSUndervoltage hysteresisRising to falling threshold100mV
VCPUVCharge pump undervoltageVCP fallingVVM + 2V
IOCPOvercurrent protectionCurrent through any FET (MODE = 0 or 330k to GND)4A
Current through any FET (MODE = 1)

8

A

Current through any FET (MODE = Hi-Z)

16

A

tOCPOvercurrent deglitch time2μs
TOTSDThermal shutdownDie temperature TJ150165180°C
THYS_OTSDThermal shutdown hysteresisDie temperature TJ20°C