SLVSFV6B August   2022  – October 2023 DRV8962

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Feature Description
    4. 7.4  Independent Half-bridge Operation
    5. 7.5  Current Sensing and Regulation
      1. 7.5.1 Current Sensing and Feedback
      2. 7.5.2 Current Sensing with External Resistor
      3. 7.5.3 Current Regulation
    6. 7.6  Charge Pump
    7. 7.7  Linear Voltage Regulator
    8. 7.8  VCC Voltage Supply
    9. 7.9  Logic Level Pin Diagram
    10. 7.10 Protection Circuits
      1. 7.10.1 VM Undervoltage Lockout (UVLO)
      2. 7.10.2 VCP Undervoltage Lockout (CPUV)
      3. 7.10.3 Logic Supply Power on Reset (POR)
      4. 7.10.4 Overcurrent Protection (OCP)
      5. 7.10.5 Thermal Shutdown (OTSD)
      6. 7.10.6 nFAULT Output
      7. 7.10.7 Fault Condition Summary
    11. 7.11 Device Functional Modes
      1. 7.11.1 Sleep Mode
      2. 7.11.2 Operating Mode
      3. 7.11.3 nSLEEP Reset Pulse
      4. 7.11.4 Functional Modes Summary
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Driving Solenoid Loads
        1. 8.1.1.1 Solenoid Driver Typical Application
        2. 8.1.1.2 Thermal Calculations
          1. 8.1.1.2.1 Power Loss Calculations
          2. 8.1.1.2.2 Junction Temperature Estimation
        3. 8.1.1.3 Application Performance Plots
      2. 8.1.2 Driving Stepper Motors
        1. 8.1.2.1 Stepper Driver Typical Application
        2. 8.1.2.2 Power Loss Calculations
        3. 8.1.2.3 Junction Temperature Estimation
      3. 8.1.3 Driving Brushed-DC Motors
        1. 8.1.3.1 Brushed-DC Driver Typical Application
        2. 8.1.3.2 Power Loss Calculation
        3. 8.1.3.3 Junction Temperature Estimation
        4. 8.1.3.4 Driving Single Brushed-DC Motor
      4. 8.1.4 Driving Thermoelectric Coolers (TEC)
      5. 8.1.5 Driving Brushless DC Motors
  10. 9 Package Thermal Considerations
    1. 9.1 DDW Package
      1. 9.1.1 Thermal Performance
        1. 9.1.1.1 Steady-State Thermal Performance
        2. 9.1.1.2 Transient Thermal Performance
    2. 9.2 DDV Package
    3. 9.3 PCB Material Recommendation
  11. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
    2. 10.2 Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

The DRV8962 is available in thermally-enhanced, 44-Pin HTSSOP packages.

  • The DDW package contains a PowerPAD™ on the bottom side of the device.

  • The DDV package contains a PowerPAD™ on the top side of the device for thermal coupling to a heatsink.

GUID-20220609-SS0I-8ZRF-BBBN-MQN3JRRCDVM4-low.svgFigure 5-1 DDW Package, Top View
GUID-20220609-SS0I-SHLB-FTQX-C6DXGP7FGFKK-low.svgFigure 5-2 DDV Package, Top View
PINTYPEDESCRIPTION
NAMEDDWDDV
VCP

1

22

Power

Charge pump output. Connect a X7R, 1-μF, 16-V ceramic capacitor from VCP to VM.

VM

2, 11, 12, 212, 11, 12, 21

Power

Power supply. Connect to motor supply voltage and bypass to PGND pins with 0.01-μF ceramic capacitors plus a bulk capacitor rated for VM.
PGND1

3

20

Power

Power ground for half-bridge 1. Connect to system ground.
PGND2

10

13

Power

Power ground for half-bridge 2. Connect to system ground.
PGND3

20

3

Power

Power ground for half-bridge 3. Connect to system ground.
PGND4

13

10

Power

Power ground for half-bridge 4. Connect to system ground.
OUT14, 5, 617, 18, 19OutputConnect to load terminal.
OUT27, 8, 914, 15, 16OutputConnect to load terminal.
OUT317, 18, 194, 5, 6OutputConnect to load terminal.
OUT414, 15, 167, 8, 9OutputConnect to load terminal.
IPROPI1

32

35

OutputCurrent sense output for half-bridge 1.
IPROPI2

31

36

Output

Current sense output for half-bridge 2.

IPROPI3

30

37

Output

Current sense output for half-bridge 3.

IPROPI4

29

38

Output

Current sense output for half-bridge 4.

EN1

37

30

Input

Enable input of half-bridge 1.

EN2

36

31

Input

Enable input of half-bridge 2.

EN3

35

32

Input

Enable input of half-bridge 3.

EN4

34

33

Input

Enable input of half-bridge 4.

IN1

41

26

InputPWM input for half-bridge 1.

IN2

40

27

InputPWM input for half-bridge 2.

IN3

39

28

Input

PWM input for half-bridge 3.

IN4

38

29

Input

PWM input for half-bridge 4.
GND

22, 23

1, 44

Power

Device ground. Connect to system ground.
CPH

44

23

PowerCharge pump switching node. Connect a X7R, 0.1-μF, VM rated ceramic capacitor from CPH to CPL.
CPL

43

24

VREF3334InputVoltage reference input for setting current regulation threshold. DVDD can be used to provide VREF through a resistor divider.
DVDD

24

43

PowerInternal LDO output. Connect a X7R, 1-μF, 6.3-V or 10-V rated ceramic capacitor to GND.
VCC

25

42

Power

Supply voltage for internal logic blocks. When separate logic supply voltage is not available, tie the VCC pin to the DVDD pin.
nFAULT

26

41

Open DrainFault indication output. Pulled logic low with fault condition. Open drain output requires an external pullup resistor.
MODE

28

39

Input

This pin programs the output rise/fall time.

OCPM

27

40

Input

Determines the fault recovery method. Depending on the OCPM voltage, fault recovery can be either latch-off or auto-retry type.

nSLEEP

42

25

Input

Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode. A narrow nSLEEP reset pulse clears latched faults.

PAD---Thermal pad.