SLVSFV6B August   2022  – October 2023 DRV8962

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Feature Description
    4. 7.4  Independent Half-bridge Operation
    5. 7.5  Current Sensing and Regulation
      1. 7.5.1 Current Sensing and Feedback
      2. 7.5.2 Current Sensing with External Resistor
      3. 7.5.3 Current Regulation
    6. 7.6  Charge Pump
    7. 7.7  Linear Voltage Regulator
    8. 7.8  VCC Voltage Supply
    9. 7.9  Logic Level Pin Diagram
    10. 7.10 Protection Circuits
      1. 7.10.1 VM Undervoltage Lockout (UVLO)
      2. 7.10.2 VCP Undervoltage Lockout (CPUV)
      3. 7.10.3 Logic Supply Power on Reset (POR)
      4. 7.10.4 Overcurrent Protection (OCP)
      5. 7.10.5 Thermal Shutdown (OTSD)
      6. 7.10.6 nFAULT Output
      7. 7.10.7 Fault Condition Summary
    11. 7.11 Device Functional Modes
      1. 7.11.1 Sleep Mode
      2. 7.11.2 Operating Mode
      3. 7.11.3 nSLEEP Reset Pulse
      4. 7.11.4 Functional Modes Summary
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Driving Solenoid Loads
        1. 8.1.1.1 Solenoid Driver Typical Application
        2. 8.1.1.2 Thermal Calculations
          1. 8.1.1.2.1 Power Loss Calculations
          2. 8.1.1.2.2 Junction Temperature Estimation
        3. 8.1.1.3 Application Performance Plots
      2. 8.1.2 Driving Stepper Motors
        1. 8.1.2.1 Stepper Driver Typical Application
        2. 8.1.2.2 Power Loss Calculations
        3. 8.1.2.3 Junction Temperature Estimation
      3. 8.1.3 Driving Brushed-DC Motors
        1. 8.1.3.1 Brushed-DC Driver Typical Application
        2. 8.1.3.2 Power Loss Calculation
        3. 8.1.3.3 Junction Temperature Estimation
        4. 8.1.3.4 Driving Single Brushed-DC Motor
      4. 8.1.4 Driving Thermoelectric Coolers (TEC)
      5. 8.1.5 Driving Brushless DC Motors
  10. 9 Package Thermal Considerations
    1. 9.1 DDW Package
      1. 9.1.1 Thermal Performance
        1. 9.1.1.1 Steady-State Thermal Performance
        2. 9.1.1.2 Transient Thermal Performance
    2. 9.2 DDV Package
    3. 9.3 PCB Material Recommendation
  11. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
    2. 10.2 Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.1 Thermal Performance

The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions.

The data in this section was simulated using the following criteria:

HTSSOP (DDW package)

  • 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (13 x 5 thermal via array, 1.1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating).
    • Top layer: HTSSOP package footprint and copper plane heatsink. Top layer copper area is varied in simulation.
    • Bottom layer: ground plane thermally connected through vias under the thermal pad for the driver. Bottom layer copper area varies with top copper area.
  • 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (13 x 5 thermal via array, 1.1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating).
    • Top layer: HTSSOP package footprint and copper plane heatsink. Top layer copper area is varied in simulation.
    • Mid layer 1: GND plane thermally connected to thermal pad through vias. The area of the ground plane varies with top copper area.
    • Mid layer 2: power plane, no thermal connection. The area of the power plane varies with top copper area.
    • Bottom layer: signal layer thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the top layer copper area.

Figure 9-1 shows an example of the simulated board for the DDW package. Table 9-1 shows the dimensions of the board that were varied for each simulation.

GUID-20230308-SS0I-5F0B-JGCB-5VZ8XJQGDDPB-low.pngFigure 9-1 DDW PCB model top layer
Table 9-1 Dimension A for DDW package
Cu area (cm2)Dimension A (mm)
219.79
426.07
8

34.63

1646.54

32

63.25