SNLS461A May 2013 – June 2015 DS110DF111
PRODUCTION DATA.
The high speed inputs and outputs have been optimized to work with interconnects using a controlled differential impedance of 100Ω. Vias should be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever differential vias are used the layout must also provide for a low inductance path for the return currents as well. Route the differential signals away from other signals and noise sources on the printed circuit board.
The typical layout example Figure 13 highlights good high-speed layout techniques.