SNLS645A August   2019  – December 2019 DS160PR410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I2C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DisplayPort Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 DC Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power
IACTIVE Device current consumption when all four channels are active All four channels enabled with VOD = L2, PWDN1,2 = L 150 200 mA
IACTIVE-HALF Device current consumption when two channels are active Two channels enabled with VOD = L2, PWDN1 or PWDN2 = L 85 112 mA
ISTBY Device current consumption in standby power mode All four channels disabled, PWDN1,2 = H 22 33 mA
VREG Internal regulator output 2.5 V
Control IO
VIH High level input voltage SDA, SCL, PWDN1, PWDN2, READ_EN_N pins 2.1 V
VIL Low level input voltage SDA, SCL, PWDN1, PWDN2, READ_EN_N pins 1.08 V
VOH High level output voltage Rpull-up = 100 kΩ (SDA, SCL, ALL_DONE_N pins) 2 V
VOL Low level output voltage IOL = –4 mA (SDA, SCL, ALL_DONE_N pins) 0.4 V
IIH Input high leakage current VInput = VDD, (SCL, SDA, PWDN1, PWDN2, READ_EN_N pins) 10 µA
IIL Input low leakage current VInput = 0 V, (SCL, SDA, PWDN1, PWDN2, READ_EN_N pins) -10 µA
CIN-CTRL Input capacitance 1.5 pF
4 Level IOs (EQ0_ADDR0, EQ1_ADDR1, EN_SMB, RX_DET, VOD, GAIN pins)
IIH_4L Input high leakage current, 4 level IOs VIN = 2.5V 10 µA
IIL_4L Input low leakage current, , 4 level IOs VIN = GND -150 µA
Receiver
ZRX-DC Rx DC Single-Ended Impedance 50 Ω
ZRX-DIFF-DC Rx DC Differential Impedance 100 Ω
Transmitter
ZTX-DIFF-DC DC Differential Tx Impedance Impedance of Tx during active signaling, VID,diff = 1Vpp 120 Ω
VTX-DC-CM Tx DC common mode Voltage 0.75 V
ITX-SHORT Tx Short Circuit Current Total current the Tx can supply when shorted to GND 90 mA