SNLS645A August   2019  – December 2019 DS160PR410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I2C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DisplayPort Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 High Speed Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receiver
RLRX-DIFF Input differential return loss with minimal channel in TI evaluation board 50 MHz to 1.25 GHz -22 dB
1.25 GHz to 2.5 GHz -19 dB
2.5 GHz to 4.0 GHz -17 dB
4.0 GHz to 8.0 GHz -14 dB
RLRX-DIFF Input differential return loss with minimal channel in TI evaluation board 8.0 GHz to 12.5 GHz -13 dB
RLRX-CM Input common-mode return loss with minimal channel in TI evaluation board 50 MHz to 2.5 GHz -18 dB
2.5 GHz to 8.0 GHz -13 dB
RLRX-CM Input common-mode return loss with minimal channel in TI evaluation board 8.0 GHz to 12.5 GHz -10 dB
XTRX Receive-side pair-to-pair isolation Minimum pair-to-pair isolation (SDD21) between two adjacent receiver pairs from 10 MHz to 8 GHz. -45 dB
GAIN CTLE block DC gain Ratio at GAIN = L3 and GAIN = L2, with low freq CK 3.0 dB
Transmitter
VODL0-L2 Ratio of VOD gain L0 to L2 GAIN = L2, with low freq CK -6 dB
VODL1-L2 Ratio of VOD gain L1 to L2 GAIN = L2, with low freq CK -3.5 dB
VODL3-L2 Ration of VOD gain L3 to L2 GAIN = L2, with low freq CK -1.5 dB
VTX-AC-CM-PP Tx AC Peak-to-Peak Common Mode Voltage Measured with lowest EQ, VOD = L2; PRBS-7, 16 Gbps, over at least 106 bits using a bandpass-Pass Filter from 30 Khz - 500 Mhz 50 mVpp
VTX-CM-DC-ACTIVE-IDLE-DELTA Absolute Delta of DC Common Mode Voltage during L0 and Electrical Idle VTX-CM-DC = |VOUTn+ + VOUTn–|/2, Measured by taking the absolute difference of VTX-CM-DC during PCIe state L0 and Electrical Idle 0 100 mV
VTX-IDLE-DIFF-AC-p AC Electrical Idle Differential Output Voltage Measured by taking the absolute difference of VOUTn+ and VOUTn– during Electrical Idle, Measured with a band-pass filter consisting of two first-order filters. The High-Pass and Low-Pass –3 dB bandwidths are 10 kHz and 1.25 GHz, respectively - zero at input 0 10 mV
VTX-RCV-DETECT Amount of Voltage change allowed during Receiver Detection Measured while Tx is sensing whether a low-impedance Receiver is present. No load is connected to the driver output 0 600 mV
RLTX-DIFF Output differential return loss with minimal channel in TI evaluation board 50 MHz to 1.25 GHz -22 dB
1.25 GHz to 2.5 GHz -20 dB
2.5 GHz to 4.0 GHz -18 dB
4.0 GHz to 8.0 GHz -15 dB
RLTX-CM Output Common-mode return loss  with minimal channel in TI evaluation board 50 MHz to 2.5 GHz -13 dB
2.5 GHz to 8.0 GHz  -11 dB
XTTX Transmit-side pair-to-pair isolation Minimum pair-to-pair isolation (SDD21) between two adjacent transmitter pairs from 10 MHz to 8 GHz. -45 dB
Device Datapath
TPLHD/PHLD Input-to-output latency (propagation delay) through a channel Measured by observing propagation delay during either Low-to-High or High-to-Low transition 70 90 ps
LTX-SKEW Lane-to-Lane Output Skew Measured between any two lanes within a single transmitter 20 ps
TRJ-DATA Additive Random Jitter with data (RMS) Difference between through redriver and baseline setup. 16 Gbps PRBS15. Minimal input/output channels.  Minimum EQ. 800 mV input. 60 110 fs
TRJ-INTRINSIC Intrinsic additive Random Jitter with clock (RMS) Difference between through redriver and baseline setup. 8Ghz clock. Minimal input/output channels.  Minimum EQ. 400mV input. 150 190 fs
TDJ-DATA Added Deterministic Jitter with data Difference between through redriver and baseline setup. 16 Gbps PRBS15. Minimal input/output channels.  Minimum EQ.. 3 5 ps
JITTERINTRINSIC-DJ Intrinsic additive Deterministic Jitter with clock Difference between through redriver and baseline setup. 8 Ghz CK. Minimal input/output channels.  Minimum EQ. 0.4 1.2 ps
JITTERINTRINSIC-TOTAL Redriver intrinsic additive Total Jitter Difference between measurement through redriver and baseline setup with 8 Ghz clock signals, lowest EQ 2.5 3.0 ps
EQGAIN8G High-frequency EQ boost @ 8 GHz Measured with maximum CTLE setting and maximum BW setting (EQ1 = L3, EQ0 = L3). Boost is defined as the gain at 8 GHz relative to 100 MHz. 18 dB
DCGAINVAR,max Maximum DC gain variation VOD=L2, GAIN=L2, min EQ setting -2.1 1.1 dB
EQGAINVAR,max Maximum EQ boost variation VOD=L2, GAIN=L2, max EQ setting, at 8 Ghz -2.9 3.5 dB
LINEARITYDC The maximum DC input amplitude for which the repeater remains linear, defined as ≤1 dB compression of Vout/Vin. VOD = L2. Minimal input channel and minimum EQ using 128T pattern at 2.5 Gbps. 800 mVpp
LINEARITYAC The maximum DC input amplitude for which the repeater remains linear, defined as ≤1 dB compression of Vout/Vin. VOD = L2. Minimal input channel and minimum EQ using 1T pattern at 16 Gbps. 750 mVpp