SNLS645A August   2019  – December 2019 DS160PR410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I2C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DisplayPort Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RNQ Package
40-Pin WQFN
Top View

Pin Functions

PIN I/O, TYPE DESCRIPTION
NAME NO.
ALL_DONE_N 8 O, 3.3 V open drain In SMBus/I2C Master Mode (EN_SMB = L1):
Indicates the completion of a valid EEPROM register load operation. External pullup resistor such as 4.7 kΩ required for operation.
High: External EEPROM load failed or incomplete
Low: External EEPROM load successful and complete
In SMBus/I2C slave/Pin Mode (EN_SMB = L3/L0):
Leave the pin floating.
EN_SMB 2 I, 4-level Four-level control input used to select SMBus/I2C or Pin control.
L0: Pin mode
L1: I2C or SMBus Master Mode
L2: RESERVED
L3: I2C or SMBus Slave Mode
EQ0_ADDR0 7 I, 4-level The 4-Level Control Input pins of DS160PR410 is defined according to Table 4.
In I2C or SMBus Mode (EN_SMB = L1 or L3), the pins are used to set the I2C or SMBus address of the device. The pin state is read on power up and decoded according to Table 5.
In Pin mode (EN_SMB = L0), the pins are decoded at power up to control the CTLE boost setting according to Table 1.
EQ1_ADDR1 6 I, 4-level
GAIN 5 I, 4-level Sets DC gain of CTLE at power up.
L0: Reserved
L1: Reserved
L2: 0 dB (recommended)
L3: 3.5 dB
GND EP P EP is the Exposed Pad at the bottom of the WQFN package. It is used as the GND return for the device. The EP should be connected to ground plane(s) through low resistance path. A via array provides a low impedance path to GND, and also improves thermal dissipation.
NC 1, 14, 15, 27, 28 — No connect
PWDN1 21 I, 3.3 V LVCMOS Two-level logic controlling the operating state of the redriver.
High: Power down for channels 0 and 1
Low: Power up, normal operation for channels 0 and 1.
PWDN2 25 I, 3.3 V LVCMOS Two-level logic controlling the operating state of the redriver.
High: Power down for channels 2 and 3
Low: Power up, normal operation for channels 2 and 3.
READ_EN_N 22 I, 3.3 V LVCMOS SMBus / I2C Master Mode (EN_SMB = L1): When asserted low, initiates the SMBus / I2C master mode EEPROM read function. When the EEPROM read is complete (indicated by assertion of ALL_DONE_N low), this pin can be held low for normal device operation.
SMBus / I2C Slave Mode (EN_SMB = L3): When asserted low, this causes the device to be held in reset (I2C state machine reset and register reset). This pin should be pulled high to 3.3 V with a external 4.7-kΩ pullup for normal operation in SMBus / I2C Slave Mode or in Pin Mode.
RSVD 24 — Reserved use for TI. The pin must be left floating (NC).
RX_DET 26 I, 4-level The RX_DET pin controls the receiver detect function. Depending on the input level, a 50 Ω or >50 kΩ termination to the power rail is enabled. See Table 3 for details.
RX0N 30 I Inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects RXP to RXN. Channel 0.
RX0P 29 I Non-inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects RXP to RXN. Channel 0.
RX1N 33 I Inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects RXP to RXN. Channel 1.
RX1P 32 I Non-inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects RXP to RXN. Channel 1.
RX2N 37 I Inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects RXP to RXN. Channel 2.
RX2P 36 I Non-inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects RXP to RXN. Channel 2.
RX3N 40 I Inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects RXP to RXN. Channel 3.
RX3P 39 I Non-inverting differential inputs to the equalizer. An on-chip, 100 Ω termination resistor connects RXP to RXN. Channel 3.
SCL 3 I/O, 3.3 V LVCMOS, open drain SMBus / I2C clock input / open-drain output. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus / I2C interface standard. This pin is 3.3 V tolerant.
SDA 4 I/O, 3.3 V LVCMOS, open drain SMBus / I2C data input / open-drain clock output. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus interface standard. This pin is 3.3 V tolerant.
TX0N 19 O Inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 0.
TX0P 20 O Non-inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 0.
TX1N 16 O Inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 1.
TX1P 17 O Non-inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 1.
TX2N 12 O Inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 2.
TX2P 13 O Non-inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 2.
TX3N 9 O Inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 3.
TX3P 10 O Non-inverting 50 Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 3.
VDD 31, 34, 35, 38 P Power supply pins. VDD = 3.3 V ±10%. The VDD pins on this device should be connected through a low-resistance path to the board VDD plane. Typical supply decoupling consists of a 0.1 µF capacitor per VDD pin and one 1.0 µF bulk capacitor per device.
VOD 23 I, 4-level Sets TX VOD setting at power up.
L0: –6 dB
L1: –3.5 dB
L2: 0 dB (recommended)
L3: –1.5 dB
VREG 11, 18 P Internal voltage regulator output. Must add decoupling caps of 0.1 µF near each pin. The regulator is only for internal use. Do not use to power any external components. Do not route the signal beyond the decoupling capacitors on board.