SNLS645A August   2019  – December 2019 DS160PR410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I2C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DisplayPort Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1.3 SMBus/I2C Master Mode Configuration (EEPROM Self Load)

To configure the DS160PR410 for SMBus master mode, set the EN_SMB pin to L1. If the DS160PR410 is configured for SMBus master mode, it will remain in the SMBus IDLE state until the READ_EN_N pin is asserted to LOW. After the READ_EN_N pin is driven LOW, the DS160PR410 becomes an SMBus master and attempts to self-configure by reading device settings stored in an external EEPROM (SMBus 8-bit address 0xA0). When the DS160PR410 has finished reading from the EEPROM successfully, it will drive the ALL_DONE_N pin LOW and then change from a SMBus master to a SMBus slave. Not all bits in the register map can be configured through an EEPROM load. Refer to the Understanding EEPROM Programming for DS160PR410 PCI Express Gen-4 Redriver application report (SNLA320) for more information.

When designing a system for using the external EEPROM, the user must follow these specific guidelines:

  • EEPROM size of 2 kb (256 × 8-bit) is recommended.
  • Set EN_SMB = L1, configure for SMBus master mode
  • The external EEPROM device address byte must be 0xA0 and capable of 400-kHz operation at 3.3-V supply

Figure 8 outlines how multiple devices can be configured through single external EEPROM device. Figure 8 shows a use case with four DS160PR410, but the user can cascade and number of DS160PR410 devices in a similar way, for brevity pullup resistors (for open-drain outputs) are not shown in the block diagram. Tie first device’s READ_EN_N pin low to automatically initiate EEPROM read at power up. Alternately the READ_EN_N pin of the first device can also be controlled by a micro-controller to initiate the EEPROM read manually. Leave the final device’s ALL_DONE_N pin floating, or connect the pin to a micro-controller input to monitor the completion of the final EEPROM read.

DS160PR410 PR410_EEPROM.gifFigure 8. Example Daisy Chain for Multiple Device Single EEPROM Configuration