SNLS685 December   2020 DS160PR412

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x8 Lane Switching
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Pin-to-pin Passive versus Redriver Option
        4. 8.2.1.4 Application Curves
      2. 8.2.2 DisplayPort Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Linear Equalization

The DS160PR412 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost to help equalize the frequency-dependent insertion loss effects of the passive channel. Table 7-1 shows available equalization boost through EQ control pins (EQ1 and EQ0), when in Pin Control mode (MODE = L0).

Table 7-1 Equalization Control Settings
EQUALIZATION SETTING TYPICAL EQ BOOST (dB)
EQ INDEX EQ1_0 (Ch 0-3) / EQ1_1 (Ch 4-7) EQ0_0 (Ch0-3) / EQ0_1 (Ch 4-7) @ 4 GHz @ 8 GHz
0 L0 L0 0.0 -0.1
1 L0 L1 1.5 4.5
2 L0 L2 2.0 5.5
3 L0 L3 2.5 6.5
4 L1 L0 2.7 7.0
5 L1 L1 3.0 8.0
6 L1 L2 4.0 9.0
7 L1 L3 5.0 10.0
8 L2 L0 6.0 11.0
9 L2 L1 7.0 12.0
10 L2 L2 7.5 12.5
11 L2 L3 8.0 13.0
12 L3 L0 8.5 14.0
13 L3 L1 9.5 15.0
14 L3 L2 10.0 16.0
15 L3 L3 11.0 17.0

The equalization of the device can also be set by writing to SMBus/I2C registers in slave mode. Refer to the DS160PR412/421 Programming Guide for details.