SNLS689 December   2020 DS160PR822

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Cross Point
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I 2 C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 37
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1.2 SMBUS/I2C Register Control Interface

If MODE = L2 (SMBus / I2C slave control mode), the DS160PR822 is configured for best signal integrity through a standard I2C or SMBus interface that may operate up to 400 kHz. The slave address of the device is determined by the pin strap settings on the ADDR1 and ADDR0 pins. Note slave addresses to access channel 0-3 and Channels 4-7 is different. Channel bank 4-7 has address which is Channel bank 0-3 address +1. The sixteen possible slave addresses (8-bit) for each channel banks of the the device are shown in Table 7-4. In SMBus/I2C modes the SCL, SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩ is a good first approximation for a bus capacitance of 50 pF.

Refer to the DS160PR822 Programming Guide (SNLU279) for register map details.
Table 7-4 SMBUS/I2C Slave Address Settings
ADDR1 ADDR0 7-bit Slave Address Channels 0-3 7-bit Slave Address Channels 4-7
L0 L0 0x18 0x19
L0 L1 0x1A 0x1B
L0 L2 0x1C 0x1D
L0 L3 0x1E 0x1F
L1 L0 0x20 0x21
L1 L1 0x22 0x23
L1 L2 0x24 0x25
L1 L3 0x26 0x27
L2 L0 0x28 0x29
L2 L1 0x2A 0x2B
L2 L2 0x2C 0x2D
L2 L3 0x2E 0x2F
L3 L0 0x30 0x31
L3 L1 0x32 0x33
L3 L2 0x34 0x35
L3 L3 0x36 0x37