SNLS689 December   2020 DS160PR822

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Cross Point
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I 2 C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 37
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Receiver Detect State Machine

The DS160PR822 deploys an RX detect state machine that governs the RX detection cycle as defined in the PCI express specifications. At power up, after a manually triggered event through PD0 and/or PD1 pins (in pin mode), or writing to the relevant I2C/SMBus register, the redriver determines whether or not a valid PCI express termination is present at the far end of the link. The RX_DET pin of DS160PR822 provides additional flexibility for system designers to appropriately set the device in desired mode according to Table 7-2. PD0 and PD1 pins impact channel groups 0-3 and 4-7 respectively. If all eight channels of DS160PR822 is used for a same PCI express link, the PD1 and PD0 pins can be shorted and driven together. For most applications the RX_DET pin can be left floating for default settings. Note mux selection pins SEL0 and SEL1 also triggers the RX detect state machine.

Table 7-2 Receiver Detect State Machine Settings
PD0 PD1 RX_DET Channels 0-3
RX Common-mode Impedance		 Channels 4-7
RX Common-mode Impedance		 COMMENTS
L L L0 Always 50Ω Always 50Ω PCI Express RX detection state machine is disabled. Recommended for non PCIe interface use case where the DS160PR822 is used as buffer with equalization.
L L L3 (Float) Pre Detect: Hi-Z
Post Detect: 50 Ω.		 Pre Detect: Hi-Z
Post Detect: 50 Ω.		 TX polls every ~150us until valid termination is detected. RX CM impedance held at Hi-Z until detection Reset by asserting PD0/1 high for 200µs then low.
H L X Hi-Z Pre Detect: Hi-Z
Post Detect: 50 Ω.		 Reset Channels 0-3 signal path and set their RX impedance to Hi-Z
L H X Pre Detect: Hi-Z
Post Detect: 50 Ω.		 Hi-Z Reset Channels 4-7 signal path and set their RX impedance to Hi-Z.
H H X Hi-Z Hi-Z