SNLS561B February   2017  – October 2019 DS250DF210

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Retimer Jitter Specifications
    7. 7.7  Timing Requirements, Retimer Specifications
    8. 7.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 7.9  Recommended SMBus Switching Characteristics (Slave Mode)
    10. 7.10 Recommended SMBus Switching Characteristics (Master Mode)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  Signal Detect
      3. 8.3.3  Continuous Time Linear Equalizer (CTLE)
      4. 8.3.4  Variable Gain Amplifier (VGA)
      5. 8.3.5  Cross-Point Switch
      6. 8.3.6  Decision Feedback Equalizer (DFE)
      7. 8.3.7  Clock and Data Recovery (CDR)
      8. 8.3.8  Calibration Clock
      9. 8.3.9  Differential Driver With FIR Filter
        1. 8.3.9.1 Setting the Output VOD, Precursor, and Postcursor Equalization
        2. 8.3.9.2 Output Driver Polarity Inversion
      10. 8.3.10 Debug Features
        1. 8.3.10.1 Pattern Generator
        2. 8.3.10.2 Pattern Checker
        3. 8.3.10.3 Eye Opening Monitor
      11. 8.3.11 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Front-Port Jitter Cleaning Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Active Cable Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Backplane and Mid-Plane Applications
      4. 9.2.4 Design Requirements
      5. 9.2.5 Detailed Design Procedure
      6. 9.2.6 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Rbaud Input data rate Full-rate 20.6 25.8 Gbps
Half-rate 10.3 12.9
Quarter-rate 5.15 6.45
tEEPROM EEPROM configuration load time Single device reading its configuration from an EEPROM. Common channel configuration. This time scales with the number of devices reading from the same EEPROM. 15(2) ms
tEEPROM EEPROM configuration load time Single device reading its configuration from an EEPROM. Unique channel configuration. This time scales with the number of devices reading from the same EEPROM. 40(2) ms
tPOR Power-on reset assertion time Internal power-on reset (PoR) stretch between stable power supply and de-assertion of internal PoR. The SMBus address is latched on the completion of the PoR stretch, and SMBus accesses are permitted. 50 ms
POWER SUPPLY
Wchannel Power consumption per active channel With CTLE, full DFE, Tx FIR, Driver and Crosspoint enabled. Idle power consumption not included. 241 305 mW
With CTLE, full DFE, Tx FIR, and Driver enabled. Crosspoint disabled.Idle power consumption not included. 233
With CTLE, partial DFE (taps 1-2 only), Tx FIR, and Driver enabled; Crosspoint and DFE taps 3-5 disabled. Idle power consumption not included. 220
With CTLE, Tx FIR, and Driver enabled; DFE disabled. Idle power consumption not included. 211 290
Assuming CDR acquiring lock with CTLE, full DFE, Tx FIR, Driver and Crosspoint enabled. Idle power consumption not included. 365 430
Assuming CDR acquiring lock with CTLE, Tx FIR, Driver and Crosspoint enabled; DFE disabled. Idle power consumption not included. 318 393
PRBS checker power consumption only(1) 220 302
PRBS generator power power consumption only(1) 230 315
Wstatic_total Total idle power consumption Idle and static mode, power supplied, no high-speed data present at inputs, all channels automatically powered down. 329 525 mW
Itotal Active mode total device supply current consumption With CTLE, full DFE, Tx FIR, and Driver enabled. 318 432 mA
With CTLE, partial DFE (taps 1-2 only), Tx FIR, and Driver enabled; DFE taps 3-5 disabled. 308
With CTLE, Tx FIR, and Driver enabled. DFE disabled. 300 421
Istatic_total Idle mode total device supply current consumption Idle and static mode. Power supplied, no high-speed data present at inputs, all channels automatically powered down. 132 200 mA
LVCMOS DC SPECIFICATIONS
VIH Input high-level voltage 2.5-V LVCMOS pins 1.75 VDD V
3.3-V LVCMOS pin (READ_EN_N) 1.75 3.6 V
VIL Input low-level voltage 2.5-V LVCMOS pins GND 0.7 V
3.3-V LVCMOS pin (READ_EN_N) GND 0.8 V
VTH High level (1) input voltage 4-level pins ADDR0, ADDR1, and EN_SMB 0.95 × VDD V
Float level input voltage 4-level pins ADDR0, ADDR1, and EN_SMB 0.67 × VDD V
10K to GND input voltage 4-level pins ADDR0, ADDR1, and EN_SMB 0.33 × VDD V
Low-level (0) input voltage 4-level pins ADDR0, ADDR1, and EN_SMB 0.1 V
VOH High-level output voltage IOH = 4 mA 2 V
VOL Low-level output voltage IOL = –4 mA 0.4 V
IIH Input high leakage current Vinput = VDD, Open-drain pins 70 μA
IIH Input high leakage current Vinput = VDD and CAL_CLK_IN pin 65 μA
IIH Input high leakage current Vinput = VDD, ADDR[1:0] and EN_SMB pins 120 μA
IIH Input high leakage current Vinput = VDD, READ_EN_N 75 μA
IIL Input low leakage current Vinput = 0 V, Open-drain pins –15 μA
IIL Input low leakage current Vinput = 0 V, CAL_CLK_IN pins –45 μA
IIL Input low leakage current Vinput = 0 V, ADDR[1:0], READ_EN_N, and EN_SMB pins –230 μA
RECEIVER INPUTS (RXnP, RXnN)
VIDMax Maximum input differential voltage For normal operation 1225 mVppd
RLSDD11 Differential input return loss, SDD11 Between 50 MHz and 3.69 GHz <–16 dB
RLSDD11 Differential input return loss, SDD11 Between 3.69 GHz and 12.9 GHz <–12 dB
RLSDC11 Differential to common-mode input return loss, SDC11 Between 50 MHz and 12.9 GHz <–23 dB
RLSCD11 Differential to common-mode input return loss, SCD11 Between 50 MHz and 12.9 GHz <–24 dB
RLSCC11 Common-mode input return loss, SCC11 Between 150 MHz and 10 GHz <–10 dB
RLSCC11 Common-mode input return loss, SCC11 Between 10 GHz and 12.9 GHz <–10 dB
VSDAT AC signal detect assert (ON) threshold level Minimum input peak-to-peak amplitude level at device pins required to assert signal detect. 25.78125 Gbps with PRBS7 pattern and 20-dB loss channel 196 mVppd
VSDDT AC signal detect de-assert (OFF) threshold level Maximum input peak-to-peak amplitude level at device pins which causes signal detect to de-assert. 25.78125 Gbps with PRBS7 pattern and 20-dB loss channel 147 mVppd
TRANSMITTER OUTPUTS (TXnP, TXnN)
VOD Output differential voltage amplitude Measured with c(0)=7 setting (Reg_0x3D[6:0]=0x07, Reg_0x3E[6:0]=0x40, REG_0x3F[6:0]=0x40). Differential measurement using an 8T pattern (eight 1s followed by eight 0s) at 25.78125 Gbps with TXPn and TXNn terminated by 50 Ω to GND. 525 mVppd
VOD Output differential voltage amplitude Measured with c(0)=31 setting (Reg_0x3D[6:0]=0x1F, Reg_0x3E[6:0]=0x40, REG_0x3F[6:0]=0x40). Differential measurement using an 8T pattern (eight 1s followed by eight 0s) at 25.78125 Gbps with TXPn and TXNn terminated by 50 Ω to GND. 1225 mVppd
VODidle Differential output amplitude with TX disabled < 11 mVppd
VODres Output VOD resolution Difference in VOD between two adjacent c(0) settings. Applies to VOD in the 525 mVppd to 1225 mVppd range [c(0)>4]. < 50 mVppd
Vcm-TX-AC Common-mode AC output noise With respect to signal ground. Measured with PRBS9 data pattern. Measured with a 33 GHz (–3 dB) low-pass filter. 6.5 mV, RMS
tr, tf Output transition time 20%-to-80% rise time and 80%-to-20% fall time on a clock-like {11111 00000} data pattern at 25.78125 Gbps. Measured for ~800 mVppd output amplitude and no equalization: Reg_0x3D=+13, Reg_0x3E=0, REG_0x3F=0 17 ps
RLSDD22 Differential output return loss, SDD22 Between 50 MHz and 5 GHz <–12 dB
RLSDD22 Differential output return loss, SDD22 Between 5 GHz and 12.9 GHz <–9 dB
RLSCD22 Common-mode to differential output return loss, SCD22 Between 50 MHz and 12.9 GHz <–22 dB
RLSDC22 Differential-to-common-mode output return loss, SDC22 Between 50 MHz and 12.9 GHz <–22 dB
RLSCC22 Common-mode output return loss, SCC22 Between 50 MHz and 10 GHz <–9 dB
RLSCC22 Common-mode output return loss, SCC22 Between 10 GHz and 12.9 GHz <–9 dB
SMBus ELECTRICAL CHARACTERISTICS (SLAVE MODE)
VIH Input high level voltage SDA and SDC 1.75 3.6 V
VIL Input low level voltage SDA and SDC GND 0.8 V
CIN Input pin capacitance 15 pF
VOL Low level output voltage SDA or SDC, IOL = 1.25 mA 0.4 V
IIN Input current SDA or SDC, VINPUT = VIN, VDD, GND –15 15 μA
TR SDA rise time, read operation Pullup resistor = 1 kΩ, Cb = 50 pF 150 ns
TF SDA fall time, read operation Pullup resistor = 1 kΩ, Cb = 50 pF 4.5 ns
(1) To ensure optimal performance, it is recommended to not enable more than two PRBS blocks (checker and/or generator) per device.
(2) From low assertion of READ_EN_N to low assertion of ALL_DONE_N. Does not include Power-On Reset time.