SNLS243 Data sheet

SNLS243H September 2006 – March 2016 DS25MB100

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

NJK|36

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Supply voltage (V_CC)		–0.3	4	V
CMOS/TTL input voltage		–0.3	V_CC + 0.3	V
CML input/output voltage		–0.3	V_CC + 0.3	V
Lead temperature	Soldering, 4 seconds		260	°C
Junction temperature			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±6000	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1250
		Machine model (MM)	±350

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

	MIN	NOM	MAX	UNIT
Supply voltage (V_CC – GND)	3.135	3.3	3.465	V
Supply noise amplitude (10 Hz to 2 GHz)			100	mV_PP
Ambient temperature	–40		85	°C
Case temperature			100	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DS25MB100	UNIT
		NJK (WQFN)
		36 PINS
R_θJA	Junction-to-ambient thermal resistance⁽²⁾	32.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	14.3	°C/W
R_θJB	Junction-to-board thermal resistance	6.2	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	6.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) Thermal resistances are based on having 16 thermal relief vias on the DAP pad under the 0 airflow condition.

6.5 Electrical Characteristics

over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER		TEST CONDITIONS			MIN	TYP⁽¹⁾	MAX	UNIT
LVCMOS DC SPECIFICATIONS
V_IH	High level input voltage				2		V_CC + 0.3	V
V_IL	Low level input voltage				–0.3		0.8	V
I_IH	High level input current	V_IN = V_CC			–10		10	µA
I_IL	Low level input current	V_IN = GND			75	94	124	µA
R_PU	Pull-high resistance					35		kΩ
RECEIVER SPECIFICATIONS
V_ID	Differential input voltage range⁽⁶⁾	AC-coupled differential signal This parameter is not tested at production	Below 1.25 Gbps		100		1750	mV_P-P
V_ID	Differential input voltage range⁽⁶⁾		Above 1.25 Gbps		100		1560	mV_P-P
V_ICM	Common-mode voltage at receiver inputs	Measured at receiver inputs reference to ground				1.3		V
R_ITD	Input differential termination⁽²⁾	On-chip differential termination between IN+ or IN−			84	100	116	Ω
DRIVER SPECIFICATIONS
V_ODB	Output differential voltage swing without pre-emphasis⁽³⁾	R_L = 100Ω ±1% DES_1=DES_0=0 DEL_1=DEL_0=0 Driver pre-emphasis disabled Running K28.7 pattern at 2.5 Gbps See Figure 6 for test circuit.			1100	1300	1500	mV_P-P
V_PE	Output pre-emphasis voltage ratio 20 × log(VODPE/VODB)	R_L = 100Ω ±1% Running K28.7 pattern at 2.5 Gbps x=S for switch side pre-emphasis control x=L for line side pre-emphasis control See Figure 9 on waveform. See Figure 6 for test circuit.	DEx_[1:0]=00			0		dB
			DEx_[1:0]=01			–3
			DEx_[1:0]=10			–6
			DEx_[1:0]=11			–9
T_PE	Pre-emphasis width	Tested at −9-dB pre-emphasis level, DEx[1:0]=11 x=S for switch side pre-emphasis control x=L for line side pre-emphasis control See Figure 3 on measurement condition.			125	188	250	ps
R_OTSE	Output termination⁽²⁾	On-chip termination from OUT+ or OUT− to V_CC			42	50	58	Ω
R_OTD	Output differential termination	On-chip differential termination between OUT+ and OUT−				100		Ω
ΔR_OTSE	Mis-match in output termination resistors	Mis-match in output terminations at OUT+ and OUT−					5%
V_OCM	Output common-mode voltage					2.7		V
POWER DISSIPATION
P_D	Power dissipation	V_DD = 3.3V at 25°C All outputs terminated by 100 Ω ±1%. DEL_[1:0]=0, DES_[1:0]=0 Running PRBS 2⁷-1 pattern at 2.5 Gbps				0.45		W
AC CHARACTERISTICS
RJ	Device random jitter⁽⁴⁾	See Figure 6 for test circuit. Alternating-1-0 pattern EQ and pre-emphasis disabled.		At 0.25 Gbps			2	ps_rms
				At 1.25 Gbps			2
				At 2.5 Gbps			2
DJ	Device deterministic jitter⁽⁵⁾	See Figure 6 for test circuit. EQ and pre-emphasis disabled Between 0.25 and 2.5 Gbps with PRBS-7 pattern for DS25MB100 at –40°C to 85°C					35	ps_p-p
DR	Data rate⁽⁶⁾	Tested with alternating 1-0 pattern			0.25		2.5	Gbps

(1) Typical parameters measured at V_CC = 3.3 V, T_A = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not ensured.

(2) IN+ and IN− are generic names refer to one of the many pairs of complimentary inputs of the DS25MB100. OUT+ and OUT− are generic names refer to one of the many pairs of the complimentary outputs of the DS25MB100. Differential input voltage V_ID is defined as |IN+–IN−|. Differential output voltage V_OD is defined as |OUT+–OUT−|.

(3) K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000}K28.5 pattern is a 20-bit repeating pattern of +K28.5 and −K28.5 code groups {110000 0101 001111 1010}

(4) Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt(RJ_OUT²– RJ_IN²), where RJ_OUT is the total random jitter measured at the output of the device in ps_rms, RJ_IN is the random jitter of the pattern generator driving the device.

(5) Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJ_OUT–DJ_IN), where DJ_OUT is the total peak-to-peak deterministic jitter measured at the output of the device in ps_p-p, DJ_IN is the peak-to-peak deterministic jitter of the pattern generator driving the device.

(6) This parameter is ensured by design and/or characterization. It is not tested in production.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
t_R	Differential low-to-high transition time	Measured with a clock-like pattern at 2.5 Gbps, between 20% and 80% of the differential output voltage. Pre-emphasis disabled. Transition time is measured with fixture as shown in Figure 6, adjusted to reflect the transition time at the output pins.	100		ps
t_F	Differential high-to-low transition time		100		ps
t_PLH	Differential low-to-high propagation delay	Measured at 50% differential voltage from input to output.		1	ns
t_PHL	Differential high-to-low propagation delay			1	ns
t_SKP	Pulse skew	\|t_PHL – t_PLH\|		20	ps
t_SKO	Output skew⁽¹⁾	Difference in propagation delay among data paths in the same device.		100	ps
t_SKPP	Part-to-part skew	Difference in propagation delay between the same output from devices operating under identical condition.		100	ps
t_SM	MUX switch time	Measured from V_IH or V_IL of the MUX-control or loopback control to 50% of the valid differential output.	1.8	6	ns

(1) t_SKO is the magnitude difference in the propagation delays among data paths. An example is the output skew among data paths from IN0± to OUT± and IN1± to OUT±. Another example is the output skew among data paths from IN± to OUT0± and IN± to OUT1±. t_SKOalso refers to the delay skew of the loopback paths of the same port and between similar data paths. An example is the output skew among data paths IN0± to OUT0± and IN1± to OUT1±.