SNLS542C October   2016  – December 2020 DS280MB810

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements – Serial Management Bus Interface
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Data Path Operation
      2. 8.3.2 AC-coupled Receiver Inputs
      3. 8.3.3 Signal Detect
      4. 8.3.4 2-Stage CTLE
      5. 8.3.5 Driver DC Gain Control
      6. 8.3.6 2x2 Cross-point Switch
      7. 8.3.7 Configurable SMBus Address
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Slave Mode Configuration
      2. 8.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 8.5 Programming
      1. 8.5.1 Transfer of Data with the SMBus Interface
    6. 8.6 Register Maps
      1. 8.6.1 Register Types: Global, Shared, and Channel
      2. 8.6.2 Global Registers: Channel Selection and ID Information
      3. 8.6.3 Shared Registers
      4. 8.6.4 Channel Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Backplane and Mid-Plane Reach Extension
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Front-Port Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Pattern Generator Characteristics
        2. 9.2.3.2 Equalizing Moderate Pre-Channel Loss
        3. 9.2.3.3 Equalizing High Pre-Channel Loss
        4. 9.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss
    3. 9.3 Initialization Set Up
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 Stripline Example
      2. 11.2.2 Microstrip Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2 Typical Application

The DS280MB810 with integrated cross-point is typically used in two main application scenarios:

  1. Backplane, mid-plane, and chip-to-chip reach extension
  2. Front-port eye opening for copper and optical applications

GUID-5F159110-20E3-4A81-8992-CA3146BE7E91-low.gifFigure 9-1 Typical application block diagram
Note:

TI recommends to AC couple the DS280MB810's high-speed outputs. In some cases, ASIC or FPGA SerDes receivers support DC coupling, and it may be desirable to DC couple the DS280MB810 output with the ASIC/FPGA RX input to reduce the PCB area which would normally be consumed by AC coupling capacitors. To DC couple the DS280MB810 output with an ASIC RX input, the ASIC RX must support DC coupling and it must support an input common mode voltage of 1.05 V. To determine if the ASIC RX supports DC coupling, here are some items to consider based on Figure 9-2:

  1. The ASIC RX must be AC coupled on-chip.
  2. The ASIC RX should not force a DC bias on the RX pins.
  3. System designers should ensure that when the PCB powers on, the power supply rails are appropriately sequenced to prevent the DS280MB810's output common mode voltage from forward-biasing the ESD structure of the ASIC or violating the absolute maximum input voltage specifications of the ASIC.

GUID-C1FC0EED-BA14-40EC-B74F-6D5D38771EB7-low.gifFigure 9-2 Considerations for DC coupling to ASIC RX