SNLS144K June   2005  – March 2024 DS40MB200

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CML Inputs and EQ
      2. 7.3.2 Multiplexer and Loopback Control
      3. 7.3.3 CML Drivers and Pre-Emphasis Control
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 CML Inputs and EQ

The high-speed inputs are self-biased to about 1.3 V at IN+ and IN- and are designed for AC coupling. See Reciever Input Termination and Bias Circuit for details about the internal receiver input termination and bias circuit.

DS40MB200 Receiver Input Termination and Bias CircuitFigure 7-1 Receiver Input Termination and Bias Circuit

The inputs are compatible to most AC coupling differential signals such as LVDS, LVPECL, and CML. The DS40MB200 is not designed to operate with data rates below 1000 Mbps or with a DC bias applied to the CML inputs or outputs. Most high-speed links are encoded for DC balance and have been defined to include AC coupling capacitors, allowing the DS40MB200 to be inserted directly into the datapath without any limitation. The ideal AC-coupling capacitor value is often based on the lowest frequency component embedded within the serial link. A typical AC-coupling capacitor value ranges between 100 and 1000 nF. Some specifications with scrambled data may require a larger capacitor for optimal performance. To reduce unwanted parasitic effects around and within the AC-coupling capacitor, a body size of 0402 is recommended. AC Test Circuit shows the AC-coupling capacitor placement in an AC test circuit.

Each input stage has a fixed equalizer that provides equalization to compensate about 5 dB (at 2 GHz) of transmission loss from a short backplane trace (about 10 inches backplane).