SNLS144K June   2005  – March 2024 DS40MB200

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CML Inputs and EQ
      2. 7.3.2 Multiplexer and Loopback Control
      3. 7.3.3 CML Drivers and Pre-Emphasis Control
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
tRDifferential low-to-high transition timeMeasured with a clock-like pattern at 100 MHz, between 20% and 80% of the differential output voltage. Pre-emphasis disabled.
Transition time is measured with fixture as shown in AC Test Circuit, adjusted to reflect the transition time at the output pins.		80ps
tFDifferential high-to-low transition time80ps
tPLHDifferential low-to-high propagation delayMeasured at 50% differential voltage from input to output.0.52ns
tPHLDifferential high-to-low propagation delay0.52ns
tSKPPulse skew(2)|tPHL–tPLH|20ps
tSKOOutput skew(3)(2)Difference in propagation delay among data paths in the same device.200ps
tSKPPPart-to-part skew(2)Difference in propagation delay between the same output from devices operating under identical condition.500ps
tSMMUX switch timeMeasured from VIH or VIL of the mux-control or loopback control to 50% of the valid differential output.1.86ns
(1) Typical parameters measured at VCC = 3.3 V, TA = 25°C. They are for reference purposes and are not production-tested.
(2) Specified by design and characterization using statistical analysis.
(3) tSKO is the magnitude difference in the propagation delays among data paths between switch A and switch B of the same port and similar data paths between port 0 and port 1. An example is the output skew among data paths from SIA_0± to LO_0±, SIB_0± to LO_0±, SIA_1± to LO_1± and SIB_1± to LO_1±. Another example is the output skew among data paths from LI_0± to SOA_0±, LI_0± to SOB_0±, LI_1± to SOA_1± and LI_1± to SOB_1±. tSKO also refers to the delay skew of the loopback paths of the same port and between similar data paths between port 0 and port 1. An example is the output skew among data paths SIA_0± to SOA_0±, SIB_0± to SOB_0±, SIA_1± to SOA_1± and SIB_1± to SOB_1±.
DS40MB200 Driver Output Transition TimeFigure 5-1 Driver Output Transition Time
DS40MB200 Propagation Delay From Input to OutputFigure 5-2 Propagation Delay From Input to Output
DS40MB200 Test Condition for Output Pre-Emphasis DurationFigure 5-3 Test Condition for Output Pre-Emphasis Duration