SNLS324F April   2011  – August 2021 DS80PCI402

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1) (1) (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics — Serial Management Bus Interface
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 15
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBUS Mode
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer of Data Through the SMBus
      3. 8.5.3 Writing a Register
      4. 8.5.4 Reading a Register
      5. 8.5.5 SMBus Controller Mode
    6. 8.6 Register Maps
      1.      31
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Considerations for Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 8-8 Multi DS80PCI402 EEPROM Data(1)
EEPROM Address Address (Hex) EEPROM Data Comments
0 00 0x43 CRC_EN = 0, Address Map = 1, >256 bytes = 0, Device Count[3:0] = 3
1 01 0x00
2 02 0x08 EEPROM Burst Size
3 03 0x00 CRC not used
4 04 0x0B Device 0 Address Location
5 05 0x00 CRC not used
6 06 0x0B Device 1 Address Location
7 07 0x00 CRC not used
8 08 0x30 Device 2 Address Location
9 09 0x00 CRC not used
10 0A 0x30 Device 3 Address Location
11 0B 0x00 Begin Device 0, 1 - Address Offset 3
12 0C 0x00
13 0D 0x04
14 0E 0x07
15 0F 0x00
16 10 0x00 EQ CHB0 = 00
17 11 0xAB VOD CHB0 = 1.0 V
18 12 0x00 DEM CHB0 = 0 (0 dB)
19 13 0x00 EQ CHB1 = 00
20 14 0x0A VOD CHB1 = 1.0 V
21 15 0xB0 DEM CHB1 = 0 (0 dB)
22 16 0x00
23 17 0x00 EQ CHB2 = 00
24 18 0xAB VOD CHB2 = 1.0 V
25 19 0x00 DEM CHB2 = 0 (0 dB)
26 1A 0x00 EQ CHB3 = 00
27 1B 0x0A VOD CHB3 = 1.0 V
28 1C 0xB0 DEM CHB3 = 0 (0 dB)
29 1D 0x01
30 1E 0x80
31 1F 0x01 EQ CHA0 = 00
32 20 0x56 VOD CHA0 = 1.0 V
33 21 0x00 DEM CHA0 = 0 (0 dB)
34 22 0x00 EQ CHA1 = 00
35 23 0x15 VOD CHA1 = 1.0 V
36 24 0x60 DEM CHA1 = 0 (0 dB)
37 25 0x00
38 26 0x01 EQ CHA2 = 00
39 27 0x56 VOD CHA2 = 1.0 V
40 28 0x00 DEM CHA2 = 0 (0 dB)
41 29 0x00 EQ CHA3 = 00
42 2A 0x15 VOD CHA3 = 1.0 V
43 2B 0x60 DEM CHA3 = 0 (0 dB)
44 2C 0x00
45 2D 0x00
46 2E 0x54
47 2F 0x54 End Device 0, 1 - Address Offset 39
48 30 0x00 Begin Device 2, 3 - Address Offset 3
49 31 0x00
50 32 0x04
51 33 0x07
52 34 0x00
53 35 0x00 EQ CHB0 = 00
54 36 0xAB VOD CHB0 = 1.0 V
55 37 0x00 DEM CHB0 = 0 (0 dB)
56 38 0x00 EQ CHB1 = 00
57 39 0x0A VOD CHB1 = 1.0 V
58 3A 0xB0 DEM CHB1 = 0 (0 dB)
59 3B 0x00
60 3C 0x00 EQ CHB2 = 00
61 3D 0xAB VOD CHB2 = 1.0 V
62 3E 0x00 DEM CHB2 = 0 (0 dB)
63 3F 0x00 EQ CHB3 = 00
64 40 0x0A VOD CHB3 = 1.0 V
65 41 0xB0 DEM CHB3 = 0 (0 dB)
66 42 0x01
67 43 0x80
68 44 0x01 EQ CHA0 = 00
69 45 0x56 VOD CHA0 = 1.0 V
70 46 0x00 DEM CHA0 = 0 (0 dB)
71 47 0x00 EQ CHA1 = 00
72 48 0x15 VOD CHA1 = 1.0 V
73 49 0x60 DEM CHA1 = 0 (0 dB)
74 4A 0x00
75 4B 0x01 EQ CHA2 = 00
76 4C 0x56 VOD CHA2 = 1.0 V
77 4D 0x00 DEM CHA2 = 0 (0 dB)
78 4E 0x00 EQ CHA3 = 00
79 4F 0x15 VOD CHA3 = 1.0 V
80 50 0x60 DEM CHA3 = 0 (0 dB)
81 51 0x00
82 52 0x00
83 53 0x54
84 54 0x54 End Device 2, 3 - Address Offset 39
(1) CRC_EN = 0, Address Map = 1, >256 byte = 0, Device Count[3:0] = 3. This example has all 8 channels set to EQ = 0x00 (min boost), VOD = 1.0 V, DEM = 0 (0 dB) and multiple device can point to the same address map.
Table 8-9 SMBus Reader MODE Register Map
Address Register Name Bit Field Type Default EEPROM Bit Description
0x00 Device Address Observation 7 Reserved R/W 0x00 Set bit to 0
6:3 Address Bit
AD[3:0]		 R Observation of AD[3:0] bits
[6]: AD3
[5]: AD2
[4]: AD1
[3]: AD0
See Table 8-6
2 EEPROM Read Done R 1: Device completed the read from external EEPROM
1:0 Reserved R/W Reserved
0x01 PWDN Channels 7:0 PWDN CHx R/W 0x00 Yes Power Down per Channel
[7]: CH7 – CHA_3
[6]: CH6 – CHA_2
[5]: CH5 – CHA_1
[4]: CH4 – CHA_0
[3]: CH3 – CHB_3
[2]: CH2 – CHB_2
[1]: CH1 – CHB_1
[0]: CH0 – CHB_0
0x00 = all channels enabled
0xFF = all channels disabled
Note: override PRSNT pin
0x02 Override PRSNT,
LPBK Control		 7 Override RXDET R/W 0x00 1 = Override Automatic Rx Detect State Machine Reset
6 RXDET Value 1 = Set Rx Detect State Machine Reset
0 = Clear Rx Detect State Machine Reset
5:4 LPBK
Control		 Yes 00: Use LPBK pin control
01: INA_n to OUTB_n loopback
10: INB_n to OUTA_n loopback
11: Disable loopback and ignore LPBK pin
3:2 Reserved Yes Set bits to 0
1 Reserved Set bit to 0
0 Override PRSNT
pin		 Yes 1: Block PRSNT pin control
0: Allow PRSNT pin control
0x03 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x04 Reserved 7:0 Reserved R/W 0x00 Yes Set bits to 0
0x05 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x06 reader Register Control 7:5 Reserved R/W 0x10 Set bits to 0
4 Reserved Yes Set bit to 1
3 Register Enable 1 = Enables SMBus Reader MODE Register Control
Note: To change VOD, DEM, and EQ of the channels in Reader mode, this bit must be set to 1.
2:0 Reserved Set bits to 0
0x07 Digital Reset Control 7 Reserved R/W 0x01 Set bit to 0
6 Reset Registers Self clearing bit, set to 1 to reset the register to default values.
5:0 Reserved Set bits to 000001'b
0x08 Override
Pin Control		 7 Reserved R/W 0x00 Set bit to 0
6 Override SD_TH Yes 1: Block SD_TH pin control
0: Allow SD_TH pin control
5 Reserved Yes Set bit to 0
4 Override IDLE Yes 1: IDLE control by registers
0: IDLE control by signal detect
3 Override RXDET Yes 1: Block RXDET pin control
0: Allow RXDET pin control
2 Override RATE Yes 1: Block RATE pin control
0: Allow RATE pin control
1:0 Reserved Set bits to 0
0x09 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x0A Signal Detect Monitor 7:0 SD_TH Status R 0x00 CH7 - CH0 Internal Signal Detector Indicator
[7]: CH7 - CHA_3
[6]: CH6 - CHA_2
[5]: CH5 - CHA_1
[4]: CH4 - CHA_0
[3]: CH3 - CHB_3
[2]: CH2 - CHB_2
[1]: CH1 - CHB_1
[0]: CH0 - CHB_0
0 = Signal detected at input (active data)
1 = Signal not detected at input (idle state)
NOTE: These bits only function when RATE pin = FLOAT.
0x0B Reserved 7 Reserved R/W 0x00 Set bits to 0
6:0 Reserved R/W 0x70 Yes Set bits to 111 0000'b
0x0C Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x0D Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x0E CH0 - CHB_0
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: Override IDLE control
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: Override IDLE control
3:2 RXDET Yes 00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-Z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is hi-Z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: Override RXDET pin
1:0 Reserved Set bits to 0
0x0F CH0 - CHB_0
EQ		 7:0 EQ Control R/W 0x2F Yes INB_0 EQ Control - total of 256 levels
See Table 8-2
0x10 CH0 - CHB_0
VOD		 7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 RATE_SEL Yes 1: Gen 1/2
0: Gen 3
Note: Override the RATE pin
5:3 Reserved Yes Set bits to default value - 101
2:0 VOD Control Yes OUTB_0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x11 CH0 - CHB_0
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH0 - CHB_0
1: RX = detected
0: RX = not detected
6:5 RATE_DET STATUS R Observation bit for RATE_DET CH0 - CHB_0
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3 Reserved R/W Set bits to 0
2:0 DEM Control R/W Yes OUTB_0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x12 CH0 - CHB_0
IDLE Threshold		 7 Reserved R/W 0x00 Yes Set bit to 0
6:4 Reserved Set bits to 0
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: Override the SD_TH pin
1:0 IDLE thd Yes Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: Override the SD_TH pin
0x13 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x14 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x15 CH1 - CHB_1
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: Override IDLE control
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: Override IDLE control
3:2 RXDET Yes 00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-Z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is hi-Z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: Override RXDET pin
1:0 Reserved Set bits to 0.
0x16 CH1 - CHB_1
EQ		 7:0 EQ Control R/W 0x2F Yes INB_1 EQ Control - total of 256 levels.
See Table 8-2
0x17 CH1 - CHB_1
VOD		 7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 RATE_SEL Yes 1: Gen 1/2
0: Gen 3
Note: Override the RATE pin
5:3 Reserved Yes Set bits to default value - 101
2:0 VOD Control Yes OUTB_1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x18 CH1 - CHB_1
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH1 - CHB_1
1: RX = detected
0: RX = not detected
6:5 RATE_DET STATUS R Observation bit for RATE_DET CH1 - CHB_1
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3 Reserved R/W Set bits to 0
2:0 DEM Control R/W Yes OUTB_1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x19 CH1 - CHB_1
IDLE Threshold		 7 Reserved R/W 0x00 Yes Set bit to 0.
6:4 Reserved Set bits to 0.
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: Override the SD_TH pin
1:0 IDLE thd Yes Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: Override the SD_TH pin
0x1A Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x1B Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x1C CH2 - CHB_2
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: Override IDLE control
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: Override IDLE control
3:2 RXDET Yes 00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-Z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is hi-Z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: Override RXDET pin
1:0 Reserved Set bits to 0
0x1D CH2 - CHB_2
EQ		 7:0 EQ Control R/W 0x2F Yes INB_2 EQ Control - total of 256 levels.
See Table 8-2
0x1E CH2 - CHB_2
VOD		 7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 RATE_SEL Yes 1: Gen 1/2
0: Gen 3
Note: Override the RATE pin
5:3 Reserved Yes Set bits to default value - 101
2:0 VOD Control Yes OUTB_2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x1F CH2 - CHB_2
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH2 - CHB_2
1: RX = detected
0: RX = not detected
6:5 RATE_DET STATUS R Observation bit for RATE_DET CH2 - CHB_2
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3 Reserved R/W Set bits to 0.
2:0 DEM Control R/W Yes OUTB_2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x20 CH2 - CHB_2
IDLE Threshold		 7 Reserved R/W 0x00 Yes Set bit to 0
6:4 Reserved Set bits to 0
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: Override the SD_TH pin.Set bits to 0
1:0 IDLE thd Yes Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: Override the SD_TH pin
0x21 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x22 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x23 CH3 - CHB_3
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: Override IDLE control
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: Override IDLE control.
3:2 RXDET Yes 00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-Z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is hi-Z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: Override RXDET pin
1:0 Reserved Set bits to 0
0x24 CH3 - CHB_3
EQ		 7:0 EQ Control R/W 0x2F Yes INB_3 EQ Control - total of 256 levels.
See Table 8-2
0x25 CH3 - CHB_3
VOD		 7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 RATE_SEL Yes 1: Gen 1/2
0: Gen 3
Note: Override the RATE pin
5:3 Reserved Yes Set bits to default value - 101
2:0 VOD Control Yes OUTB_3 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x26 CH3 - CHB_3
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH3 - CHB_3
1: RX = detected
0: RX = not detected
6:5 RATE_DET STATUS R Observation bit for RATE_DET CH3 - CHB_3
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3 Reserved R/W Set bits to 0
2:0 DEM Control R/W Yes OUTB_3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x27 CH3 - CHB_3
IDLE Threshold		 7 Reserved R/W 0x00 Yes Set bit to 0
6:4 Reserved Set bits to 0
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: Override the SD_TH pin
1:0 IDLE thd Yes Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: Override the SD_TH pin
0x28 Signal Detect
Status Control		 7 Reserved R/W 0x0C Set bit to 0
6 Reserved Yes Set bit to 0
5:4 High SD_TH Status Yes Enable Higher Range of Signal Detect Status Thresholds
[5]: CH0 - CH3
[4]: CH4 - CH7
3:2 Fast Signal Detect Status Yes Enable Fast Signal Detect Status
[3]: CH0 - CH3
[2]: CH4 - CH7
Note: In Fast Signal Detect, assert/deassert response occurs after approximately 3-4 ns
1:0 Reduced SD Status Gain Yes Enable Reduced Signal Detect Status Gain
[1]: CH0 - CH3
[0]: CH4 - CH7
0x29 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x2A Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x2B CH4 - CHA_0
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: Override IDLE control
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: Override IDLE control
3:2 RXDET Yes 00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-Z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is hi-Z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: Override RXDET pin
1:0 Reserved Set bits to 0
0x2C CH4 - CHA_0
EQ		 7:0 EQ Control R/W 0x2F Yes INA_0 EQ Control - total of 256 levels
See Table 8-2
0x2D CH4 - CHA_0
VOD		 7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 RATE_SEL Yes 1: Gen 1/2
0: Gen 3
Note: Override the RATE pin
5:3 Reserved Yes Set bits to default value - 101
2:0 VOD Control Yes OUTA_0 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x2E CH4 - CHA_0
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH4 - CHA_0
1: RX = detected
0: RX = not detected
6:5 RATE_DET STATUS R Observation bit for RATE_DET CH4 - CHA_0
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3 Reserved R/W Set bits to 0
2:0 DEM Control R/W Yes OUTA_0 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x2F CH4 - CHA_0
IDLE Threshold		 7 Reserved R/W 0x00 Yes Set bit to 0
6:4 Reserved Set bits to 0
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: Override the SD_TH pin
1:0 IDLE thd Yes Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: Override the SD_TH pin
0x30 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x31 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x32 CH5 - CHA_1
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: Override IDLE control
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: Override IDLE control
3:2 RXDET Yes 00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-Z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is hi-Z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: override RXDET pin
1:0 Reserved Set bits to 0
0x33 CH5 - CHA_1
EQ		 7:0 EQ Control R/W 0x2F Yes INA_1 EQ Control - total of 256 levels
See Table 8-2
0x34 CH5 - CHA_1
VOD		 7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 RATE_SEL Yes 1: Gen 1/2
0: Gen 3
Note: Override the RATE pin
5:3 Reserved Yes Set bits to default value - 101
2:0 VOD Control Yes OUTA_1 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x35 CH5 - CHA_1
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH5 - CHA_1
1: RX = detected
0: RX = not detected
6:5 RATE_DET STATUS R Observation bit for RATE_DET CH5 - CHA_1
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3 Reserved R/W Set bits to 0
2:0 DEM Control R/W Yes OUTA_1 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x36 CH5 - CHA_1
IDLE Threshold		 7 Reserved R/W 0x00 Yes Set bit to 0
6:4 Reserved Set bits to 0
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: Override the SD_TH pin
1:0 IDLE thd Yes Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: Override the SD_TH pin
0x37 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x38 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x39 CH6 - CHA_2
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: Override IDLE control
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: Override IDLE control
3:2 RXDET Yes 00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-Z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is hi-Z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: Override RXDET pin
1:0 Reserved Set bits to 0
0x3A CH6 - CHA_2
EQ		 7:0 EQ Control R/W 0x2F Yes INA_2 EQ Control - total of 256 levels
See Table 8-2
0x3B CH6 - CHA_2
VOD		 7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 RATE_SEL Yes 1: Gen 1/2
0: Gen 3
Note: Override the RATE pin
5:3 Reserved Yes Set bits to default value - 101
2:0 VOD Control Yes OUTA_2 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x3C CH6 - CHA_2
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH6 - CHA_2
1: RX = detected
0: RX = not detected
6:5 RATE_DET STATUS R Observation bit for RATE_DET CH6 - CHA_2
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3 Reserved R/W Set bits to 0
2:0 DEM Control R/W Yes OUTA_2 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x3D CH6 - CHA_2
IDLE Threshold		 7 Reserved R/W 0x00 Yes Set bit to 0
6:4 Reserved Set bits to 0
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: Override the SD_TH pin
1:0 IDLE thd Yes Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: Override the SD_TH pin
0x3E Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x3F Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x40 CH7 - CHA_3
IDLE, RXDET		 7:6 Reserved R/W 0x00 Set bits to 0
5 IDLE_AUTO Yes 1 = Allow IDLE_SEL control in bit 4
0 = Automatic IDLE detect
Note: Override IDLE control
4 IDLE_SEL Yes 1: Output is MUTED (electrical idle)
0: Output is ON
Note: Override IDLE control
3:2 RXDET Yes 00: Input is hi-Z impedance
01: Auto RX-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-Z until detection; once detected input termination is 50 Ω
10: Auto RX-Detect,
outputs test every 12 ms until detection occurs; termination is hi-Z until detection; once detected input termination is 50 Ω
11: Input is 50 Ω
Note: Override RXDET pin
1:0 Reserved Set bits to 0
0x41 CH7 - CHA_3
EQ		 7:0 EQ Control R/W 0x2F Yes INA_3 EQ Control - total of 256 levels
See Table 8-2
0x42 CH7 - CHA_3
VOD		 7 Short Circuit Protection R/W 0xAD Yes 1: Enable the short circuit protection
0: Disable the short circuit protection
6 RATE_SEL Yes 1: Gen 1/2
0: Gen 3
Note: Override the RATE pin
5:3 Reserved Yes Set bits to default value - 101
2:0 VOD Control Yes OUTA_3 VOD Control
000: 0.7 V
001: 0.8 V
010: 0.9 V
011: 1.0 V
100: 1.1 V
101: 1.2 V (default)
110: 1.3 V
111: 1.4 V
0x43 CH7 - CHA_3
DEM		 7 RXDET STATUS R 0x02 Observation bit for RXDET CH7 - CHA_3
1: RX = detected
0: RX = not detected
6:5 RATE_DET STATUS R Observation bit for RATE_DET CH7 - CHA_3
00: GEN1 (2.5G)
01: GEN2 (5G)
11: GEN3 (8G)
4:3 Reserved R/W Set bits to 0
2:0 DEM Control R/W Yes OUTA_3 DEM Control
000: 0 dB
001: –1.5 dB
010: –3.5 dB (default)
011: –5 dB
100: –6 dB
101: –8 dB
110: –9 dB
111: –12 dB
0x44 CH7 - CHA_3
IDLE Threshold		 7 Reserved R/W 0x00 Yes Set bit to 0
6:4 Reserved Set bits to 0
3:2 IDLE tha Yes Assert threshold
00 = 180 mVp-p (default)
01 = 160 mVp-p
10 = 210 mVp-p
11 = 190 mVp-p
Note: Override the SD_TH pin
1:0 IDLE thd Yes Deassert threshold
00 = 110 mVp-p (default)
01 = 100 mVp-p
10 = 150 mVp-p
11 = 130 mVp-p
Note: Override the SD_TH pin
0x45 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x46 Reserved 7:0 Reserved R/W 0x38 Set bits to 0x38
0x47 Reserved 7:4 Reserved R/W 0x00 Set bits to 0
3:0 Reserved R/W Yes Set bits to 0
0x48 Reserved 7:6 Reserved R/W 0x05 Yes Set bits to 0
5:0 Reserved R/W Set bits to 00 0101'b
0x49 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x4A Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x4B Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x4C Reserved 7:3 Reserved R/W 0x00 Yes Set bits to 0
2:1 Reserved R/W Set bits to 0
0 Reserved R/W Yes Set bits to 0
0x4D Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x4E Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x4F Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x50 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x51 Device ID 7:5 VERSION R 0x44 010'b
4:0 ID 00100'b
0x52 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x53 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x54 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x55 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x56 Reserved 7:0 Reserved R/W 0x10 Set bits to 0x10
0x57 Reserved 7:0 Reserved R/W 0x64 Set bits to 0x64
0x58 Reserved 7:0 Reserved R/W 0x21 Set bits to 0x21
0x59 Reserved 7:1 Reserved R/W 0x00 Set bits to 0
0 Reserved Yes Set bit to 0
0x5A Reserved 7:0 Reserved R/W 0x54 Yes Set bits to 0x54
0x5B Reserved 7:0 Reserved R/W 0x54 Yes Set bits to 0x54
0x5C Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x5D Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x5E Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x5F Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x60 Reserved 7:0 Reserved R/W 0x00 Set bits to 0
0x61 Reserved 7:0 Reserved R/W 0x00 Set bits to 0