SNLS324F April   2011  – August 2021 DS80PCI402

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1) (1) (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics — Serial Management Bus Interface
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 15
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBUS Mode
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer of Data Through the SMBus
      3. 8.5.3 Writing a Register
      4. 8.5.4 Reading a Register
      5. 8.5.5 SMBus Controller Mode
    6. 8.6 Register Maps
      1.      31
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Considerations for Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 4-Level Input Configuration Guidelines

The 4-level input pins use a resistor divider to help set the four valid levels. There is an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the package pin. These resistors, together with the external resistor connection combine to achieve the desired voltage level. Using the 1-kΩ pullup, 1-kΩ pulldown, no connect, or 20-kΩ pulldown provide the optimal voltage levels for each of the four input states.

Table 8-1 4-Level Input Voltage
LEVEL SETTING 3.3-V MODE 2.5-V MODE
0 1 kΩ to GND 0.1 V 0.08 V
R 20 kΩ to GND 0.33 × VIN 0.33 × VDD
F FLOAT 0.67 × VIN 0.67 × VDD
1 1 kΩ to VDD/VIN VIN – 0.05 V VDD – 0.04 V

Typical 4-level input thresholds:

  • Level 1 to 2 = 0.2 VIN or VDD
  • Level 2 to 3 = 0.5 VIN or VDD
  • Level 3 to 4 = 0.8 VIN or VDD

To minimize the start-up current associated with the integrated 2.5-V regulator, the 1-kΩ pullup and pulldown resistors are recommended. If several 4-level inputs require the same setting, it is possible to combine two or more 1-kΩ resistors into a single lower value resistor. As an example; combining two inputs with a single 500-Ω resistor is a good way to save board space. For the 20 kΩ to GND, this should also scale to 10 kΩ.

Table 8-2 Equalizer Settings(1)
EQUALIZATION BOOST RELATIVE TO DC
LEVEL EQA1
EQB1		 EQA0
EQB0		 EQ – 8 BITS [7:0] dB at
1.25 GHz		 dB at
2.5 GHz		 dB at
4 GHz		 SUGGESTED USE
1 0 0 0000 0000 = 0x00 2.1 3.7 4.9 FR4 < 5 inch trace
2 0 R 0000 0001 = 0x01 3.4 5.8 7.9 FR4 5 inch 5–mil trace
3 0 Float 0000 0010 = 0x02 4.8 7.7 9.9 FR4 5 inch 4–mil trace
4 0 1 0000 0011 = 0x03 5.9 8.9 11.0 FR4 10 inch 5–mil trace
5 R 0 0000 0111 = 0x07 7.2 11.2 14.3 FR4 10 inch 4–mil trace
6 R R 0001 0101 = 0x15 6.1 11.4 14.6 FR4 15 inch 4–mil trace
7 R Float 0000 1011 = 0x0B 8.8 13.5 17.0 FR4 20 inch 4–mil trace
8 R 1 0000 1111 = 0x0F 10.2 15.0 18.5 FR4 25 to 30 inch 4–mil trace
9 Float 0 0101 0101 = 0x55 7.5 12.8 18.0 FR4 30 inch 4–mil trace
10 Float R 0001 1111 = 0x1F 11.4 17.4 22.0 FR4 35 inch 4–mil trace
11 Float Float 0010 1111 = 0x2F 13.0 19.7 24.4 10 m, 30-awg cable
12 Float 1 0011 1111 = 0x3F 14.2 21.1 25.8 10 m – 12m cable
13 1 0 1010 1010 = 0xAA 13.8 21.7 27.4
14 1 R 0111 1111 = 0x7F 15.6 23.5 29.0
15 1 Float 1011 1111 = 0xBF 17.2 25.8 31.4
16 1 1 1111 1111 = 0xFF 18.4 27.3 32.7
(1) The suggested equalizer CTLE settings are based on 0 dB of TX preshoot/de-emphasis. In PCIe Gen 3 applications which use TX preshoot/de-emphasis, the CTLE should be set to a lower boost setting to optimize the RX eye opening.
Table 8-3 Output Voltage and De-Emphasis Settings(1)
LEVEL DEMA1
DEMB1		 DEMA0
DEMB0		 VOD Vp-p DEM dB
(see (1))		 INNER AMPLITUDE
Vp-p		 SUGGESTED USE
1 0 0 0.8 0 0.8 FR4 < 5 inch 4-mil trace
2 0 R 0.9 0 0.9 FR4 < 5 inch 4-mil trace
3 0 Float 0.9 –3.5 0.6 FR4 10 inch 4-mil trace
4 0 1 1.0 0 1.0 FR4 < 5 inch 4-mil trace
5 R 0 1.0 –3.5 0.7 FR4 10 inch 4-mil trace
6 R R 1.0 –6 0.5 FR4 15 inch 4-mil trace
7 R Float 1.1 0 1.1 FR4 < 5 inch 4-mil trace
8 R 1 1.1 –3.5 0.7 FR4 10 inch 4-mil trace
9 Float 0 1.1 –6 0.6 FR4 15 inch 4-mil trace
10 Float R 1.2 0 1.2 FR4 < 5 inch 4-mil trace
11 Float Float 1.2 –3.5 0.8 FR4 10 inch 4-mil trace
12 Float 1 1.2 –6 0.6 FR4 15 inch 4-mil trace
13 1 0 1.3 0 1.3 FR4 < 5 inch 4-mil trace
14 1 R 1.3 –3.5 0.9 FR4 10 inch 4-mil trace
15 1 Float 1.3 –6 0.7 FR4 15 inch 4-mil trace
16 1 1 1.3 –9 0.5 FR4 20 inch 4-mil trace
(1) The VOD output amplitude and DEM de-emphasis levels are set with the DEMA/B[1:0] pins.
The de-emphasis levels are available in GEN1, GEN2, and GEN 3 modes when RATE = Float.
Table 8-4 RX-Detect Settings
PRSNT(1)
(PIN 52)		 RXDET
(PIN 22)		 SMBus REG
BIT[3:2]		 INPUT TERMINATION COMMENTS
0 0 00 Hi-Z Manual RX-Detect, input is high-impedance mode
0 Tie 20 kΩ
to GND		 01 Pre Detect: Hi-Z
Post Detect: 50 Ω		 Auto RX-Detect, outputs test every 12 ms for 600 ms then stops; termination is hi-Z until detection; once detected input termination is 50 Ω
Reset function by pulsing PRSNT high for 5 µs then low again
0 Float
(Default)		 10 Pre Detect: Hi-Z
Post Detect: 50 Ω		 Auto RX-Detect, outputs test every 12 ms until detection occurs; termination is hi-Z until detection; once detected input termination is 50 Ω
Reset function by pulsing PRSNT high for 5 µs then low again
0 1 11 50 Ω Manual RX-Detect, input is 50 Ω
1 X Hi-Z Power-down mode, input is high impedance, output drivers are disabled

Used to reset RX-Detect State Machine when held high for 5 µs
(1) In SMBus Reader MODE, the Rx Detect State Machine can be manually reset in software by overriding the device PRSNT function. This is accomplished by setting the Override RXDET bit (Reg 0x02[7]) and then toggling the RXDET Value bit (Reg 0x02[6]). See Table 8-9 for more information about resetting the Rx Detect State Machine.
Table 8-5 Signal Detect Threshold Level(1)
SD_TH SMBus REG BIT [3:2] AND [1:0] ASSERT LEVEL (TYP) DEASSERT LEVEL (TYP)
0 10 210 mVp-p 150 mVp-p
R 01 160 mVp-p 100 mVp-p
F (default) 00 180 mVp-p 110 mVp-p
1 11 190 mVp-p 130 mVp-p
(1) VDD = 2.5 V, 25° C, and 0101 pattern at 8 Gbps.