SNLS401C February   2012  – September 2018 DS90C187

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
      2.      Typical Application
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     DS90C187 Pin Descriptions — Serializer
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended Input Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 AC Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Device Functional Modes
      1. 8.3.1  Device Configuration
      2. 8.3.2  Single Pixel Input / Single Pixel Output
      3. 8.3.3  Single Pixel Input / Dual Pixel Output
      4. 8.3.4  Dual Pixel Input / Dual Pixel Output
      5. 8.3.5  Pixel Clock Edge Select (RFB)
      6. 8.3.6  Power Management
      7. 8.3.7  Sleep Mode (PDB)
      8. 8.3.8  LVDS Outputs
      9. 8.3.9  18 bit / 24 bit Color Mode (18B)
      10. 8.3.10 LVCMOS Inputs
    4. 8.4 Programming
      1. 8.4.1 LVDS Interface / TFT Color Data Recommended Mapping
        1. 8.4.1.1 Color Mapping Information
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LVDS Interconnect Guidelines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Up Sequence
    2. 10.2 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 LVDS Interface / TFT Color Data Recommended Mapping

Different color mapping options exist. Check with the color mapping of the Deserializer / TCON device that is used to ensure compatible mapping for the application. The DS90C187 supports three modes of operation for single and dual pixel applications supporting either 24bpp or 18bpp color depths.

In the Dual Pixel / 24bpp mode, eight LVDS data lines are provided along with two LVDS clock lines (8D+2C). The Deserializer may utilize one or two clock lines. The 53 bit interface typically assigns 24 bits to RGB for the odd pixel, 24 bits to RGB for the even pixel, 3 bits for the video control signals (HS, VS and DE), 1 bit for odd pixel and 1 bit for even pixel which can be ignored or used for general purpose data, control or L/R signaling.

A reduced width input interface is also supported with a Single-to-Dual Pixel conversion where the data is presented at double rate (same clock edge, 2X speed, see ) and the DE transition is used to flag the first pixel. Also note in both 8D+2C configurations, the three video control signals are sent over both the A and B outputs. The DES / TCON may recover one set, or both depending upon its implementation. The Dual Pixel / 24bpp 8D+2C LVDS Interface Mapping is shown in .

A Dual Pixel / 18bpp mode is also supported. In this configuration OA3 and OB3 LVDS output channels are placed in TRI-STATE® to save power. Their respective inputs are ignored. (Figure 15)

In the Single Pixel / 24bpp mode, four LVDS data lines are provided along with a LVDS clock line (4D+C). The 28 bit interface typically assigns 24 bits to RGB color data, 3 bits to video control (HS, VS and DE) and one spare bit can be ignored, used for L/R signaling or function as a general purpose bit. The Single Pixel / 24bpp 4D+C LVDS Interface Mapping is shown in .

A Single Pixel / 18bpp mode is also supported. In this configuration the OA3 LVDS output channel is placed in TRI-STATE® to save power. Its respective inputs are ignored. (Figure 17)

DS90C187 30151676.gifFigure 14. Dual Pixel / 24bpp LVDS Mapping
DS90C187 30151677.gifFigure 15. Dual Pixel / 18bpp LVDS Mapping
DS90C187 30151679.gifFigure 16. Single Pixel / 24bpp LVDS Mapping
DS90C187 30151678.gifFigure 17. Single Pixel / 18bpp LVDS Mapping