SNLS141E August   2002  – March 2024 DS90LT012A , DS90LV012A

PRODUCTION DATA  

  1.   1
  2. Features
  3. Description
  4. Pin Configuration and Functions
  5. Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Recommended Operating Conditions
    3. 4.3 Electrical Characteristics
    4. 4.4 Switching Characteristics
  6. Parameter Measurement Information
  7. Detailed Description
    1. 6.1 Functional Block Diagram
    2. 6.2 Feature Description
      1. 6.2.1 Termination
      2. 6.2.2 Threshold
      3. 6.2.3 Fail-Safe Feature
      4. 6.2.4 Probing LVDS Transmission Lines
    3. 6.3 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
  9. Power Supply Recommendations
  10. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Differential Traces
    3. 9.3 Cables and Connectors, General Comments
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Switching Characteristics

over operating free-air temperature range (unless otherwise noted)(1)(2)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tPHLDDifferential Propagation Delay High to LowCL = 15 pF1.01.83.5ns
tPLHDDifferential Propagation Delay Low to HighVID = 200 mV1.01.73.5ns
tSKD1Differential Pulse Skew |tPHLD − tPLHD| (3)(Figure 5-1 and Figure 5-2)0100400ps
tSKD3Differential Part to Part Skew (4)00.31.0ns
tSKD4Differential Part to Part Skew (5)00.41.5ns
tTLHRise Time350800ps
tTHLFall Time175800ps
fMAXMaximum Operating Frequency (6)200250MHz
CL includes probe and jig capacitance.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤ 3 ns for IN±.
tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.
tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range.
tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.
fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.4V), load = 15 pF (stray plus probes). The parameter is ensured by design. The limit is based on the statistical analysis of the device over the PVT range by the transition times (tTLH and tTHL).
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. Section 4.3 specifies conditions of device operation.
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as VID).
ESD Ratings:
  • DS90LV012A:
    • HBM (1.5 kΩ, 100 pF) ≥ 2kV
    • EIAJ (0Ω, 200 pF) ≥ 900V
    • CDM ≥ 2000V
    • IEC direct (330Ω, 150 pF) ≥ 5kV
  • DS90LT012A:
    • HBM (1.5 kΩ, 100 pF) ≥ 2kV
    • EIAJ (0Ω, 200 pF) ≥ 700V
    • CDM ≥ 2000V
    • IEC direct (330Ω, 150 pF) ≥ 7kV
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification.
VDD is always higher than IN+ and IN− voltage. IN+ and IN− are allowed to have voltage range −0.05V to +2.35V when VDD = 2.7V and |VID| / 2 to VDD − 0.3V when VDD = 3.0V to 3.6V. VID is not allowed to be greater than 100 mV when VCM = 0.05V to 2.35V when VDD = 2.7V or when VCM = |VID| / 2 to VDD − 0.3V when VDD = 3.0V to 3.6V.