SNLS013F June 1998 – June 2016 DS90LV028A
PRODUCTION DATA.
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 20. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100 Ω. A termination resistor of 100 Ω (selected to match the media), and is placed as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be considered.
The DS90LV028A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1-V common mode range centered around 1.2 V. This is related to the driver offset voltage which is typically 1.2 V. The driven signal is centered around this voltage and may shift ±1 V around this center point. The ±1-V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common mode effects of coupled noise, or a combination of the two. The AC parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0 V to 2.4 V (measured from each pin to ground). The device operates for receiver input voltages up to VCC, but exceeding VCC turns on the ESD protection circuitry which clamps the bus voltages.
The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20 mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as a valid signal.
The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs.
External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors must be in the 5-kΩ to 15-kΩ range to minimize loading and waveform distortion to the driver. The common mode bias point must be set to approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry. Refer to AN-1194 Failsafe Biasing of LVDS Interfaces (SNLA051) for more information.
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use must have a matched differential impedance of about 100 Ω. They must not introduce major impedance discontinuities.
Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common mode (not differential mode) noise which is rejected by the receiver.
For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤ d ≤ 10 M, CAT 3 (category 3) twisted pair cable works well, is readily available, and relatively inexpensive.
Table 1 lists the functional modes of the DS90LV028A.
INPUTS | OUTPUT |
---|---|
[RIN+] − [RIN−] | ROUT |
VID ≥ 0.1 V | H |
VID ≤ −0.1 V | L |
Full fail-safe OPEN/SHORT or Terminated | H |