SNLS013 Data sheet

SNLS013F June 1998 – June 2016 DS90LV028A

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

D|8
- MSOI002K
NGN|8
- MPDS401A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage, V_CC		–0.3	4	V
Input voltage, R_IN+, R_IN−		–0.3	3.9	V
Output voltage, R_OUT		–0.3	V_CC + 0.3	V
Maximum package power dissipation at 25°C	D package		1025	mW
	Derate D package		8.2 mW/°C above 25°C	°C
	NGN package		3.3	W
	Derate NGN package		25.6 mW/°C above 25°C	°C
Lead temperature range, soldering (4 s)			260	°C
Junction temperature, T_J			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±7000	V
V_(ESD)	Electrostatic discharge	Machine model (MM)⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) EIAJ, 0 Ω, 200 pF

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_CC	Supply voltage	3	3.3	3.6	V
	Receiver input voltage	GND		3	V
T_A	Operating free-air temperature	–40	25	85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾			DS90LV028A		UNIT
			D (SOIC)	NGN (WSON)
			8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance		—	35.9	°C/W
		Low-K thermal resistance	212	—
		High-K thermal resistance	122	—
R_θJC(top)	Junction-to-case (top) thermal resistance		69.1	24.2	°C/W
R_θJB	Junction-to-board thermal resistance		47.7	13.2	°C/W
ψ_JT	Junction-to-top characterization parameter		15.2	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter		47.2	13.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance		—	2.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS		MIN	TYP⁽²⁾	MAX	UNIT
V_TH	Differential input high threshold	V_CM = 1.2 V, 0 V, 3 V, R_IN+, R_IN− pins⁽³⁾				100	mV
V_TL	Differential input low threshold	V_CM = 1.2 V, 0 V, 3 V, R_IN+, R_IN− pins⁽³⁾		–100			mV
I_IN	Input current	V_CC = 3.6 V or 0 V, R_IN+, R_IN− pins	V_IN = 2.8 V	–10	±1	10	μA
		V_CC = 3.6 V or 0 V, R_IN+, R_IN− pins	V_IN = 0 V	–10	±1	10
		V_CC = 0 V, V_IN = 3.6 V, R_IN+, R_IN− pins		–20		20
V_OH	Output high voltage	I_OH = –0.4 mA, V_ID = 200 mV, R_OUT pin		2.7	3.1		V
		I_OH = –0.4 mA, inputs terminated, R_OUT pin		2.7	3.1
		I_OH = –0.4 mA, inputs shorted, R_OUT pin		2.7	3.1
V_OL	Output low voltage	I_OL = 2 mA, V_ID = –200 mV, R_OUT pin			0.3	0.5	V
I_OS	Output short-circuit current	V_OUT = 0 V, R_OUT pin⁽⁴⁾		–15	–50	–100	mA
V_CL	Input clamp voltage	I_CL = –18 mA, R_OUT pin		–1.5	–0.8		V
I_CC	No load supply current	V_CC pin, inputs open			5.4	9	mA

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as V_ID).

(2) All typicals are given for: V_CC = 3.3 V and T_A = 25°C.

(3) V_CC is always higher than R_IN+ and R_IN− voltage. R_IN+ and R_IN− are allowed to have voltage range –0.05 V to 3.05 V. V_ID is not allowed to be greater than 100 mV when V_CM = 0 V or 3 V.

(4) Output short circuit current (I_OS) is specified as magnitude only, minus sign indicates direction only. Only one output must be shorted at a time, do not exceed maximum junction temperature specification.

6.6 Switching Characteristics

V_CC = 3.3 V ±10%, and T_A = −40°C to 85°C (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PHLD	Differential propagation delay high to low	C_L = 15 pF	1	1.6	2.5	ns
t_PLHD	Differential propagation delay low to high	V_ID = 200 mV	1	1.7	2.5	ns
t_SKD1	Differential pulse skew \|t_PHLD − t_PLHD\|⁽³⁾	See Figure 18 and Figure 19	0	50	400	ps
t_SKD2	Differential channel-to-channel skew-same device⁽⁴⁾		0	0.1	0.5	ns
t_SKD3	Differential part to part skew⁽⁵⁾		0		1	ns
t_SKD4	Differential part to part skew⁽⁶⁾		0		1.5	ns
t_TLH	Rise Time			325	800	ps
t_THL	Fall Time			225	800	ps
f_MAX	Maximum operating frequency⁽⁷⁾		200	250		MHz

(1) C_L includes probe and jig capacitance.

(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O = 50 Ω, t_r and t_f (0% to 100%) ≤ 3 ns for R_IN.

(3) t_SKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.

(4) t_SKD2 is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple receivers within the integrated circuit.

(5) t_SKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V_CC and within 5°C of each other within the operating temperature range.

(6) t_SKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. t_SKD4 is defined as |Maximum − Minimum| differential propagation delay.

(7) f_MAX generator input conditions: t_r = t_f < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle, V_OL (max 0.4V), V_OH (min 2.7V), load = 15 pF (stray plus probes).