SNLS707 February   2023 DS90UB635-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended Timing for the Serial Control Bus
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CSI-2 Receiver
        1. 7.3.1.1 CSI-2 Receiver Operating Modes
        2. 7.3.1.2 CSI-2 Receiver High-Speed Mode
        3. 7.3.1.3 CSI-2 Protocol Layer
        4. 7.3.1.4 CSI-2 Short Packet
        5. 7.3.1.5 CSI-2 Long Packet
        6. 7.3.1.6 CSI-2 Errors and Detection
          1. 7.3.1.6.1 CSI-2 ECC Detection and Correction
          2. 7.3.1.6.2 CSI-2 Check Sum Detection
          3. 7.3.1.6.3 D-PHY Error Detection
          4. 7.3.1.6.4 CSI-2 Receiver Status
      2. 7.3.2 FPD-Link III Forward Channel Transmitter
        1. 7.3.2.1 Frame Format
      3. 7.3.3 FPD-Link III Back Channel Receiver
      4. 7.3.4 Serializer Status and Monitoring
        1. 7.3.4.1 Forward Channel Diagnostics
        2. 7.3.4.2 Back Channel Diagnostics
        3. 7.3.4.3 Voltage and Temperature Sensing
          1. 7.3.4.3.1 Programming Example
        4. 7.3.4.4 Built-In Self Test
      5. 7.3.5 FrameSync Operation
        1. 7.3.5.1 External FrameSync
        2. 7.3.5.2 Internally Generated FrameSync
      6. 7.3.6 GPIO Support
        1. 7.3.6.1 GPIO Status
        2. 7.3.6.2 GPIO Input Control
        3. 7.3.6.3 GPIO Output Control
        4. 7.3.6.4 Forward Channel GPIO
        5. 7.3.6.5 Back Channel GPIO
      7. 7.3.7 Unique ID
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clocking Modes
        1. 7.4.1.1 Synchronous Mode
        2. 7.4.1.2 Non-Synchronous Clock Mode
        3. 7.4.1.3 Non-Synchronous Internal Mode
        4. 7.4.1.4 DVP Backwards Compatibility Mode
        5. 7.4.1.5 Configuring CLK_OUT
      2. 7.4.2 MODE
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Configuration
        1. 7.5.1.1 IDX
      2. 7.5.2 I2C Interface Operation
      3. 7.5.3 I2C Timing
    6. 7.6 Pattern Generation
      1. 7.6.1 Reference Color Bar Pattern
      2. 7.6.2 Fixed Color Patterns
      3. 7.6.3 Packet Generator Programming
        1. 7.6.3.1 Determining Color Bar Size
      4. 7.6.4 Code Example for Pattern Generator
    7. 7.7 Register Maps
      1. 7.7.1  I2C Device ID Register
      2. 7.7.2  Reset
      3. 7.7.3  General Configuration
      4. 7.7.4  Forward Channel Mode Selection
      5. 7.7.5  BC_MODE_SELECT
      6. 7.7.6  PLL Clock Control
      7. 7.7.7  Clock Output Control 0
      8. 7.7.8  Clock Output Control 1
      9. 7.7.9  Back Channel Watchdog Control
      10. 7.7.10 I2C Control 1
      11. 7.7.11 I2C Control 2
      12. 7.7.12 SCL High Time
      13. 7.7.13 SCL Low Time
      14. 7.7.14 Local GPIO DATA
      15. 7.7.15 GPIO Input Control
      16. 7.7.16 DVP_CFG
      17. 7.7.17 DVP_DT
      18. 7.7.18 Force BIST Error
      19. 7.7.19 Remote BIST Control
      20. 7.7.20 Sensor Voltage Gain
      21. 7.7.21 Sensor Temp Gain
      22. 7.7.22 Sensor Control 0
      23. 7.7.23 Sensor Control 1
      24. 7.7.24 Voltage Sensor 0 Thresholds
      25. 7.7.25 Voltage Sensor 1 Thresholds
      26. 7.7.26 Temperature Sensor Thresholds
      27. 7.7.27 CSI-2 Alarm Enable
      28. 7.7.28 Alarm Sense Enable
      29. 7.7.29 Back Channel Alarm Enable
      30. 7.7.30 CSI-2 Polarity Select
      31. 7.7.31 CSI-2 LP Mode Polarity
      32. 7.7.32 CSI-2 High-Speed RX Enable
      33. 7.7.33 CSI-2 Low Power Enable
      34. 7.7.34 CSI-2 Termination Enable
      35. 7.7.35 CSI-2 Packet Header Control
      36. 7.7.36 Back Channel Configuration
      37. 7.7.37 Datapath Control 1
      38. 7.7.38 Remote Partner Capabilities 1
      39. 7.7.39 Partner Deserializer ID
      40. 7.7.40 Target 0 ID
      41. 7.7.41 Target 1 ID
      42. 7.7.42 Target 2 ID
      43. 7.7.43 Target 3 ID
      44. 7.7.44 Target 4 ID
      45. 7.7.45 Target 5 ID
      46. 7.7.46 Target 6 ID
      47. 7.7.47 Target 7 ID
      48. 7.7.48 Target 0 Alias
      49. 7.7.49 Target 1 Alias
      50. 7.7.50 Target 2 Alias
      51. 7.7.51 Target 3 Alias
      52. 7.7.52 Target 4 Alias
      53. 7.7.53 Target 5 Alias
      54. 7.7.54 Target 6 Alias
      55. 7.7.55 Target 7 Alias
      56. 7.7.56 Back Channel Control
      57. 7.7.57 Revision ID
      58. 7.7.58 Device Status
      59. 7.7.59 General Status
      60. 7.7.60 GPIO Pin Status
      61. 7.7.61 BIST Error Count
      62. 7.7.62 CRC Error Count 1
      63. 7.7.63 CRC Error Count 2
      64. 7.7.64 Sensor Status
      65. 7.7.65 Sensor V0
      66. 7.7.66 Sensor V1
      67. 7.7.67 Sensor T
      68. 7.7.68 CSI-2 Error Count
      69. 7.7.69 CSI-2 Error Status
      70. 7.7.70 CSI-2 Errors Data Lanes 0 and 1
      71. 7.7.71 CSI-2 Errors Data Lanes 2 and 3
      72. 7.7.72 CSI-2 Errors Clock Lane
      73. 7.7.73 CSI-2 Packet Header Data
      74. 7.7.74 Packet Header Word Count 0
      75. 7.7.75 Packet Header Word Count 1
      76. 7.7.76 CSI-2 ECC
      77. 7.7.77 IND_ACC_CTL
      78. 7.7.78 IND_ACC_ADDR
      79. 7.7.79 IND_ACC_DATA
      80. 7.7.80 FPD3_TX_ID0
      81. 7.7.81 FPD3_TX_ID1
      82. 7.7.82 FPD3_TX_ID2
      83. 7.7.83 FPD3_TX_ID3
      84. 7.7.84 FPD3_TX_ID4
      85. 7.7.85 FPD3_TX_ID5
      86. 7.7.86 Indirect Access Registers
        1. 7.7.86.1  PGEN_CTL
        2. 7.7.86.2  PGEN_CFG
        3. 7.7.86.3  PGEN_CSI_DI
        4. 7.7.86.4  PGEN_LINE_SIZE1
        5. 7.7.86.5  PGEN_LINE_SIZE0
        6. 7.7.86.6  PGEN_BAR_SIZE1
        7. 7.7.86.7  PGEN_BAR_SIZE0
        8. 7.7.86.8  PGEN_ACT_LPF1
        9. 7.7.86.9  PGEN_ACT_LPF0
        10. 7.7.86.10 PGEN_TOT_LPF1
        11. 7.7.86.11 PGEN_TOT_LPF0
        12. 7.7.86.12 PGEN_LINE_PD1
        13. 7.7.86.13 PGEN_LINE_PD0
        14. 7.7.86.14 PGEN_VBP
        15. 7.7.86.15 PGEN_VFP
        16. 7.7.86.16 PGEN_COLOR0
        17. 7.7.86.17 PGEN_COLOR1
        18. 7.7.86.18 PGEN_COLOR2
        19. 7.7.86.19 PGEN_COLOR3
        20. 7.7.86.20 PGEN_COLOR4
        21. 7.7.86.21 PGEN_COLOR5
        22. 7.7.86.22 PGEN_COLOR6
        23. 7.7.86.23 PGEN_COLOR7
        24. 7.7.86.24 PGEN_COLOR8
        25. 7.7.86.25 PGEN_COLOR9
        26. 7.7.86.26 PGEN_COLOR10
        27. 7.7.86.27 PGEN_COLOR11
        28. 7.7.86.28 PGEN_COLOR12
        29. 7.7.86.29 PGEN_COLOR13
        30. 7.7.86.30 PGEN_COLOR14
        31. 7.7.86.31 PGEN_COLOR15
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power-over-Coax
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 CSI-2 Interface
        2. 8.2.2.2 FPD-Link III Input / Output
        3. 8.2.2.3 Internal Regulator Bypassing
        4. 8.2.2.4 Loop Filter Decoupling
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequencing
      1. 9.1.1 System Initialization
    2. 9.2 Power Down (PDB)
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CSI-2 Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.1 Power-over-Coax

The DS90UB635-Q1 is designed to support the Power-over-Coax (PoC) method of powering remote sensor systems. With this method, the power is delivered over the same medium (a coaxial cable) used for high-speed digital video data, bidirectional control, and diagnostics data transmission. This method uses passive networks or filters that isolate the transmission line from the loading of the DC-DC regulator circuits and their connecting power traces on both sides of the link as shown in #SNLS47910566.

GUID-268ED3A1-D614-4EB9-944A-269017122CDD-low.gifFigure 8-1 Power-over-Coax (PoC) System Diagram

The PoC networks' impedance of ≥ 1 kΩ over a specific frequency band is recommended to isolate the transmission line from the loading of the regulator circuits. Higher PoC network impedance will contribute to favorable insertion loss and return loss characteristics in the high-speed channel. The lower limit of the frequency band is defined as ½ of the frequency of the back channel, fBC. The upper limit of the frequency band is the frequency of the forward high-speed channel, fFC. However, the main criteria that need to be met in the high-speed channel, which consists of a serializer PCB, a deserializer PCB, and a cable, are the insertion loss and return loss limits defined in the Total Channel Requirements(1) over the entire system, while the system is under maximum current load and extreme temperature conditions (2).

  1. Contact TI for more information on the required Channel Specifications defined for each individual FPD-Link device.
  2. The PoC network and any components along the high-speed trace on the PCB will contribute to the PCB loss budget. TI has recommendations for the loss budget allocation for each individual PCB and cable component in the overall high-speed channel, but the loss limits defined for the total channel in the Channel Specifications must be met.

#SNLS47910566A shows an example PoC network suitable for a "4G" FPD-Link III consisting of DS90UB635-Q1 and DS90UB638-Q1 or DS90UB662-Q1 pair with the bidirectional channel operating at 50 Mbps (½ fBCC = 25 MHz) and the forward channel operating at 4.16 Gbps (fFC ≈ 2.1 GHz). Other PoC networks are possible and may be different on the serializer and the deserializer boards as long as the printed-circuit board return loss requirements listed in Table 8-2 are met.

GUID-EAD1721D-ADDB-451B-A9E9-F07208A429F6-low.gifFigure 8-2 Typical PoC Network for a "4G" FPD-Link III

Table 8-1 lists essential components for this particular PoC network. Note that the impedance characteristic of the ferrite beads deviates with the bias current. Therefore, keeping the current going through the network below 150 mA is recommended.

Table 8-1 Suggested Components for a "4G" FPD-Link III PoC Network
COUNTREF DESDESCRIPTIONPART NUMBERMFR
1L1Inductor, 10 µH, 0.288 Ω maximum, 530 mA minimum (Isat, Itemp)
30 MHz SRF minimum, 3 mm × 3 mm, General-Purpose		LQH3NPN100MJRMurata
Inductor, 10 µH, 0.288 Ω maximum, 530 mA minimum (Isat, Itemp)
30 MHz SRF minimum, 3 mm × 3 mm, AEC-Q200		LQH3NPZ100MJRMurata
Inductor, 10 µH, 0.360 Ω maximum, 450 mA minimum (Isat, Itemp)
30 MHz SRF minimum, 3.2 mm × 2.5 mm, AEC-Q200		NLCV32T-100K-EFDTDK
Inductor, 10 µH, 0.400 Ω typical, 550 mA minimum (Isat, Itemp)
39 MHz SRF typical, 3 mm × 3 mm, AEC-Q200		TYS3010100M-10Laird
Inductor, 10 µH, 0.325 Ω maximum, 725 mA minimum (Isat, Itemp)
41 MHz SRF typical, 3 mm × 3 mm, AEC-Q200		TYS3015100M-10Laird
3FB1-FB3Ferrite Bead, 1.5 kΩ at 1 GHz, 0.5 Ω maximum at DC
500 mA at 85°C, 0603 SMD , General-Purpose		BLM18HE152SN1Murata
Ferrite Bead, 1.5 kΩ at 1 GHz, 0.5 Ω maximum at DC
500 mA at 85°C, 0603 SMD , AEC-Q200		BLM18HE152SZ1Murata

In addition to the selection of PoC network components, their placement and layout play a critical role as well.

  • Place the smallest component, typically a ferrite bead or a chip inductor, as close to the connector as possible. Route the high-speed trace through one of its pads to avoid stubs.
  • Use the smallest component pads as allowed by manufacturer's design rules. Add anti-pads in the inner planes below the component pads to minimize impedance drop.
  • Consult with the connector manufacturer for optimized connector footprint. If the connector is mounted on the same side as the IC, minimize the impact of the through-hole connector stubs by routing the high-speed signal traces on the opposite side of the connector mounting side.
  • Use coupled 100-Ω differential signal traces from the device pins to the AC-coupling caps. Use 50-Ω single-ended traces from the AC-coupling capacitors to the connector.
  • Terminate the inverting signal traces close to the connectors with standard 49.9-Ω resistors.

The suggested characteristics for single-ended PCB traces (microstrips or striplines) for serializer or deserializer boards are listed in Table 8-2. The effects of the PoC networks must be accounted for when testing the traces for compliance to the suggested limits.

Table 8-2 Suggested Characteristics for Single-Ended PCB Traces With Attached PoC Networks
PARAMETERMINTYPMAXUNIT
LtraceSingle-ended PCB trace length from the device pin to the connector pin5cm
ZtraceSingle-ended PCB trace characteristic impedance455055Ω
ZconConnector (mounted) characteristic impedance405060Ω

The VPOC fluctuations on the serializer side, caused by the transient current draw of the sensor, the DC resistance of cables, and PoC components, must be kept to a minimum as well. Increasing the VPOC voltage and adding extra decoupling capacitance (> 10 µF) help reduce the amplitude and slew rate of the VPOC fluctuations.