SNLS707 February   2023 DS90UB635-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended Timing for the Serial Control Bus
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CSI-2 Receiver
        1. 7.3.1.1 CSI-2 Receiver Operating Modes
        2. 7.3.1.2 CSI-2 Receiver High-Speed Mode
        3. 7.3.1.3 CSI-2 Protocol Layer
        4. 7.3.1.4 CSI-2 Short Packet
        5. 7.3.1.5 CSI-2 Long Packet
        6. 7.3.1.6 CSI-2 Errors and Detection
          1. 7.3.1.6.1 CSI-2 ECC Detection and Correction
          2. 7.3.1.6.2 CSI-2 Check Sum Detection
          3. 7.3.1.6.3 D-PHY Error Detection
          4. 7.3.1.6.4 CSI-2 Receiver Status
      2. 7.3.2 FPD-Link III Forward Channel Transmitter
        1. 7.3.2.1 Frame Format
      3. 7.3.3 FPD-Link III Back Channel Receiver
      4. 7.3.4 Serializer Status and Monitoring
        1. 7.3.4.1 Forward Channel Diagnostics
        2. 7.3.4.2 Back Channel Diagnostics
        3. 7.3.4.3 Voltage and Temperature Sensing
          1. 7.3.4.3.1 Programming Example
        4. 7.3.4.4 Built-In Self Test
      5. 7.3.5 FrameSync Operation
        1. 7.3.5.1 External FrameSync
        2. 7.3.5.2 Internally Generated FrameSync
      6. 7.3.6 GPIO Support
        1. 7.3.6.1 GPIO Status
        2. 7.3.6.2 GPIO Input Control
        3. 7.3.6.3 GPIO Output Control
        4. 7.3.6.4 Forward Channel GPIO
        5. 7.3.6.5 Back Channel GPIO
      7. 7.3.7 Unique ID
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clocking Modes
        1. 7.4.1.1 Synchronous Mode
        2. 7.4.1.2 Non-Synchronous Clock Mode
        3. 7.4.1.3 Non-Synchronous Internal Mode
        4. 7.4.1.4 DVP Backwards Compatibility Mode
        5. 7.4.1.5 Configuring CLK_OUT
      2. 7.4.2 MODE
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Configuration
        1. 7.5.1.1 IDX
      2. 7.5.2 I2C Interface Operation
      3. 7.5.3 I2C Timing
    6. 7.6 Pattern Generation
      1. 7.6.1 Reference Color Bar Pattern
      2. 7.6.2 Fixed Color Patterns
      3. 7.6.3 Packet Generator Programming
        1. 7.6.3.1 Determining Color Bar Size
      4. 7.6.4 Code Example for Pattern Generator
    7. 7.7 Register Maps
      1. 7.7.1  I2C Device ID Register
      2. 7.7.2  Reset
      3. 7.7.3  General Configuration
      4. 7.7.4  Forward Channel Mode Selection
      5. 7.7.5  BC_MODE_SELECT
      6. 7.7.6  PLL Clock Control
      7. 7.7.7  Clock Output Control 0
      8. 7.7.8  Clock Output Control 1
      9. 7.7.9  Back Channel Watchdog Control
      10. 7.7.10 I2C Control 1
      11. 7.7.11 I2C Control 2
      12. 7.7.12 SCL High Time
      13. 7.7.13 SCL Low Time
      14. 7.7.14 Local GPIO DATA
      15. 7.7.15 GPIO Input Control
      16. 7.7.16 DVP_CFG
      17. 7.7.17 DVP_DT
      18. 7.7.18 Force BIST Error
      19. 7.7.19 Remote BIST Control
      20. 7.7.20 Sensor Voltage Gain
      21. 7.7.21 Sensor Temp Gain
      22. 7.7.22 Sensor Control 0
      23. 7.7.23 Sensor Control 1
      24. 7.7.24 Voltage Sensor 0 Thresholds
      25. 7.7.25 Voltage Sensor 1 Thresholds
      26. 7.7.26 Temperature Sensor Thresholds
      27. 7.7.27 CSI-2 Alarm Enable
      28. 7.7.28 Alarm Sense Enable
      29. 7.7.29 Back Channel Alarm Enable
      30. 7.7.30 CSI-2 Polarity Select
      31. 7.7.31 CSI-2 LP Mode Polarity
      32. 7.7.32 CSI-2 High-Speed RX Enable
      33. 7.7.33 CSI-2 Low Power Enable
      34. 7.7.34 CSI-2 Termination Enable
      35. 7.7.35 CSI-2 Packet Header Control
      36. 7.7.36 Back Channel Configuration
      37. 7.7.37 Datapath Control 1
      38. 7.7.38 Remote Partner Capabilities 1
      39. 7.7.39 Partner Deserializer ID
      40. 7.7.40 Target 0 ID
      41. 7.7.41 Target 1 ID
      42. 7.7.42 Target 2 ID
      43. 7.7.43 Target 3 ID
      44. 7.7.44 Target 4 ID
      45. 7.7.45 Target 5 ID
      46. 7.7.46 Target 6 ID
      47. 7.7.47 Target 7 ID
      48. 7.7.48 Target 0 Alias
      49. 7.7.49 Target 1 Alias
      50. 7.7.50 Target 2 Alias
      51. 7.7.51 Target 3 Alias
      52. 7.7.52 Target 4 Alias
      53. 7.7.53 Target 5 Alias
      54. 7.7.54 Target 6 Alias
      55. 7.7.55 Target 7 Alias
      56. 7.7.56 Back Channel Control
      57. 7.7.57 Revision ID
      58. 7.7.58 Device Status
      59. 7.7.59 General Status
      60. 7.7.60 GPIO Pin Status
      61. 7.7.61 BIST Error Count
      62. 7.7.62 CRC Error Count 1
      63. 7.7.63 CRC Error Count 2
      64. 7.7.64 Sensor Status
      65. 7.7.65 Sensor V0
      66. 7.7.66 Sensor V1
      67. 7.7.67 Sensor T
      68. 7.7.68 CSI-2 Error Count
      69. 7.7.69 CSI-2 Error Status
      70. 7.7.70 CSI-2 Errors Data Lanes 0 and 1
      71. 7.7.71 CSI-2 Errors Data Lanes 2 and 3
      72. 7.7.72 CSI-2 Errors Clock Lane
      73. 7.7.73 CSI-2 Packet Header Data
      74. 7.7.74 Packet Header Word Count 0
      75. 7.7.75 Packet Header Word Count 1
      76. 7.7.76 CSI-2 ECC
      77. 7.7.77 IND_ACC_CTL
      78. 7.7.78 IND_ACC_ADDR
      79. 7.7.79 IND_ACC_DATA
      80. 7.7.80 FPD3_TX_ID0
      81. 7.7.81 FPD3_TX_ID1
      82. 7.7.82 FPD3_TX_ID2
      83. 7.7.83 FPD3_TX_ID3
      84. 7.7.84 FPD3_TX_ID4
      85. 7.7.85 FPD3_TX_ID5
      86. 7.7.86 Indirect Access Registers
        1. 7.7.86.1  PGEN_CTL
        2. 7.7.86.2  PGEN_CFG
        3. 7.7.86.3  PGEN_CSI_DI
        4. 7.7.86.4  PGEN_LINE_SIZE1
        5. 7.7.86.5  PGEN_LINE_SIZE0
        6. 7.7.86.6  PGEN_BAR_SIZE1
        7. 7.7.86.7  PGEN_BAR_SIZE0
        8. 7.7.86.8  PGEN_ACT_LPF1
        9. 7.7.86.9  PGEN_ACT_LPF0
        10. 7.7.86.10 PGEN_TOT_LPF1
        11. 7.7.86.11 PGEN_TOT_LPF0
        12. 7.7.86.12 PGEN_LINE_PD1
        13. 7.7.86.13 PGEN_LINE_PD0
        14. 7.7.86.14 PGEN_VBP
        15. 7.7.86.15 PGEN_VFP
        16. 7.7.86.16 PGEN_COLOR0
        17. 7.7.86.17 PGEN_COLOR1
        18. 7.7.86.18 PGEN_COLOR2
        19. 7.7.86.19 PGEN_COLOR3
        20. 7.7.86.20 PGEN_COLOR4
        21. 7.7.86.21 PGEN_COLOR5
        22. 7.7.86.22 PGEN_COLOR6
        23. 7.7.86.23 PGEN_COLOR7
        24. 7.7.86.24 PGEN_COLOR8
        25. 7.7.86.25 PGEN_COLOR9
        26. 7.7.86.26 PGEN_COLOR10
        27. 7.7.86.27 PGEN_COLOR11
        28. 7.7.86.28 PGEN_COLOR12
        29. 7.7.86.29 PGEN_COLOR13
        30. 7.7.86.30 PGEN_COLOR14
        31. 7.7.86.31 PGEN_COLOR15
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power-over-Coax
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 CSI-2 Interface
        2. 8.2.2.2 FPD-Link III Input / Output
        3. 8.2.2.3 Internal Regulator Bypassing
        4. 8.2.2.4 Loop Filter Decoupling
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequencing
      1. 9.1.1 System Initialization
    2. 9.2 Power Down (PDB)
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CSI-2 Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RHB Package
32-Pin VQFN
Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
CSI INTERFACE
CSI_CLKP 5 I, DPHY CSI-2 clock input pins. Connect to a CSI-2 clock source with matched 100-Ω (±5%) impedance interconnects.
CSI_CLKN 6 I, DPHY
CSI_D0P 3 I, DPHY CSI-2 data input pins. Connect to a CSI-2 data sources with matched 100-Ω (±5%) impedance interconnects. If unused, these pins may be left floating.
CSI_D0N 4 I, DPHY
CSI_D1P 1 I, DPHY
CSI_D1N 2 I, DPHY
CSI_D2P 31 I, DPHY
CSI_D2N 32 I, DPHY
CSI_D3P 29 I, DPHY
CSI_D3N 30 I, DPHY
SERIAL CONTROL INTERFACE
I2C_SDA 23 OD I2C Data and Clock Pins. Typically pulled up by 470-Ω to 4.7-kΩ resistors to either 1.8-V or 3.3-V supply rail depending on IDX setting. See I2C Interface Configuration for further details on the I2C implementation of the DS90UB635-Q1.
I2C_SCL 24 OD
CONFIGURATION and CONTROL
RES0 7 I Reserved pin – Connect to GND
RES1 22 I Reserved pin – Do not connect (leave floating)
PDB 8 I, PD Power-down inverted Input Pin. Internal 1-MΩ pulldown. Typically connected to processor GPIO with pull down. When PDB input is brought HIGH, the device is enabled and internal register and state machines are reset to default values. Asserting PDB signal low will power down the device and consume minimum power. The default function of this pin is PDB = LOW; POWER DOWN. PDB should remain low until after power supplies are applied and reach minimum required levels. See Power Down (PDB) for further details on the function of PDB.
PDB INPUT IS NOT 3.3-V TOLERANT.
PDB = 1.8 V, device is enabled (normal operation)
PDB = 0, device is powered down.
MODE 21 I, S Mode select configuration input. Default operational mode will be strapped at start-up based on the MODE input voltage when PDB transitions LOW to HIGH. Typically connected to voltage divider through external pullup to VDD18 and pulldown to GND applying an appropriate bias voltage. See MODE for details.
CLK_OUT/IDX 19 I/O, S IDX pin sets the I2C pullup voltage and device address; connect to external pullup to VDD and pulldown to GND to create a voltage divider. When PDB transitions LOW to HIGH, the strap input voltage is sensed at the CLOCK_OUT/IDX pin to determine functionality and then converted to CLK_OUT. See I2C Interface Configuration for details. If CLK_OUT is used, the minimum resistance on the pin is 35 kΩ. If unused, CLK_OUT/IDX may be tied to GND.
FPD-LINK III INTERFACE
DOUT- 13 I/O FPD-Link III Input/Output pins. These pins must be AC-coupled. See GUID-DE356548-6DAB-40F2-82CD-442C0128ADF1.html#SNLS4791057A and GUID-DE356548-6DAB-40F2-82CD-442C0128ADF1.html#SNLS4791056 for typical connection diagrams and Table 8-3 for recommended capacitor values.
DOUT+ 14 I/O
POWER AND GROUND
VDDD_CAP 26 D, P A connection for an internal analog regulator decoupling capacitor. Typically connected to 10-µF, 0.1-µF, and 0.01-µF capacitors to GND. Do not connect to an external supply rail. See Typical Application for more details.
VDDDRV_CAP 15 D, P A connection for an internal analog regulator decoupling capacitor. Typically connected to 10-µF, 0.1-µF, and 0.01-µF capacitors to GND. Do not connect to an external supply rail. See Typical Application for more details.
VDDPLL_CAP 10 D, P A connection for an internal analog regulator decoupling capacitor. Typically connected to 10-µF, 0.1-µF, and 0.01-µF capacitors to GND. Do not connect to an external supply rail. See Typical Application for more details.
VDDD 25 P 1.8-V (±5%) Power Supply pin.
Typically connected to 1-µF and 0.01-µF capacitors to GND.
VDDDRV 16 P 1.8-V (±5%) Analog Power Supply pin.
Typically connected to 1-µF and 0.01-µF capacitors to GND.
VDDPLL 11 P 1.8-V (±5%) Analog Power Supply pin.
Typically connected to 1-µF and 0.01-µF capacitors to GND.
GND DAP G DAP is the large metal contact at the bottom side, located at the center of the VQFN package. Connect to the ground plane (GND).
LOOP FILTER
LPF1 9 P Loop Filter 1: Connect as described in GUID-76E4FDF5-E188-430D-97F8-5386174D9F74.html#GUID-76E4FDF5-E188-430D-97F8-5386174D9F74.
LPF2 12 P Loop Filter 2: Connect as described in GUID-76E4FDF5-E188-430D-97F8-5386174D9F74.html#GUID-76E4FDF5-E188-430D-97F8-5386174D9F74.
CLOCK INTERFACE AND GPIO
GPIO_0 17 I/O, PD General-Purpose Input/Output pins. These pins can also be configured to sense the voltage at their inputs. See Voltage and Temperature Sensing. At power up, these GPIO pins default to inputs with a 300-kΩ (typical) internal pulldown resistor. These pins may be left floating if unused, but TI recommends to set the GPIOx_INPUT_EN to 0 to disable the pins. See GUID-87E219D5-4674-4BB0-AEAD-F4F953F586FC.html#GUID-87E219D5-4674-4BB0-AEAD-F4F953F586FC for programmability.
GPIO_1 18 I/O, PD
GPIO_2 27 I/O, PD General-Purpose Input/Output pins. At power up, these GPIO pins default to inputs with a 300-kΩ (typical) internal pulldown resistor. These pins may be left floating if unused, but TI recommends to set the GPIOx_INPUT_EN to 0 to disable the pins. See GUID-87E219D5-4674-4BB0-AEAD-F4F953F586FC.html#GUID-87E219D5-4674-4BB0-AEAD-F4F953F586FC for programmability.
GPIO_3 28 I/O. PD
CLKIN 20 I Reference Clock Input pin. If operating in non-sync external clock mode, connect this pin to a local clock source. If unused (like other clocking modes), this pin may be left open. See Table 7-8 for more information on clocking modes.