SNLS707 February   2023 DS90UB635-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended Timing for the Serial Control Bus
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CSI-2 Receiver
        1. 7.3.1.1 CSI-2 Receiver Operating Modes
        2. 7.3.1.2 CSI-2 Receiver High-Speed Mode
        3. 7.3.1.3 CSI-2 Protocol Layer
        4. 7.3.1.4 CSI-2 Short Packet
        5. 7.3.1.5 CSI-2 Long Packet
        6. 7.3.1.6 CSI-2 Errors and Detection
          1. 7.3.1.6.1 CSI-2 ECC Detection and Correction
          2. 7.3.1.6.2 CSI-2 Check Sum Detection
          3. 7.3.1.6.3 D-PHY Error Detection
          4. 7.3.1.6.4 CSI-2 Receiver Status
      2. 7.3.2 FPD-Link III Forward Channel Transmitter
        1. 7.3.2.1 Frame Format
      3. 7.3.3 FPD-Link III Back Channel Receiver
      4. 7.3.4 Serializer Status and Monitoring
        1. 7.3.4.1 Forward Channel Diagnostics
        2. 7.3.4.2 Back Channel Diagnostics
        3. 7.3.4.3 Voltage and Temperature Sensing
          1. 7.3.4.3.1 Programming Example
        4. 7.3.4.4 Built-In Self Test
      5. 7.3.5 FrameSync Operation
        1. 7.3.5.1 External FrameSync
        2. 7.3.5.2 Internally Generated FrameSync
      6. 7.3.6 GPIO Support
        1. 7.3.6.1 GPIO Status
        2. 7.3.6.2 GPIO Input Control
        3. 7.3.6.3 GPIO Output Control
        4. 7.3.6.4 Forward Channel GPIO
        5. 7.3.6.5 Back Channel GPIO
      7. 7.3.7 Unique ID
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clocking Modes
        1. 7.4.1.1 Synchronous Mode
        2. 7.4.1.2 Non-Synchronous Clock Mode
        3. 7.4.1.3 Non-Synchronous Internal Mode
        4. 7.4.1.4 DVP Backwards Compatibility Mode
        5. 7.4.1.5 Configuring CLK_OUT
      2. 7.4.2 MODE
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Configuration
        1. 7.5.1.1 IDX
      2. 7.5.2 I2C Interface Operation
      3. 7.5.3 I2C Timing
    6. 7.6 Pattern Generation
      1. 7.6.1 Reference Color Bar Pattern
      2. 7.6.2 Fixed Color Patterns
      3. 7.6.3 Packet Generator Programming
        1. 7.6.3.1 Determining Color Bar Size
      4. 7.6.4 Code Example for Pattern Generator
    7. 7.7 Register Maps
      1. 7.7.1  I2C Device ID Register
      2. 7.7.2  Reset
      3. 7.7.3  General Configuration
      4. 7.7.4  Forward Channel Mode Selection
      5. 7.7.5  BC_MODE_SELECT
      6. 7.7.6  PLL Clock Control
      7. 7.7.7  Clock Output Control 0
      8. 7.7.8  Clock Output Control 1
      9. 7.7.9  Back Channel Watchdog Control
      10. 7.7.10 I2C Control 1
      11. 7.7.11 I2C Control 2
      12. 7.7.12 SCL High Time
      13. 7.7.13 SCL Low Time
      14. 7.7.14 Local GPIO DATA
      15. 7.7.15 GPIO Input Control
      16. 7.7.16 DVP_CFG
      17. 7.7.17 DVP_DT
      18. 7.7.18 Force BIST Error
      19. 7.7.19 Remote BIST Control
      20. 7.7.20 Sensor Voltage Gain
      21. 7.7.21 Sensor Temp Gain
      22. 7.7.22 Sensor Control 0
      23. 7.7.23 Sensor Control 1
      24. 7.7.24 Voltage Sensor 0 Thresholds
      25. 7.7.25 Voltage Sensor 1 Thresholds
      26. 7.7.26 Temperature Sensor Thresholds
      27. 7.7.27 CSI-2 Alarm Enable
      28. 7.7.28 Alarm Sense Enable
      29. 7.7.29 Back Channel Alarm Enable
      30. 7.7.30 CSI-2 Polarity Select
      31. 7.7.31 CSI-2 LP Mode Polarity
      32. 7.7.32 CSI-2 High-Speed RX Enable
      33. 7.7.33 CSI-2 Low Power Enable
      34. 7.7.34 CSI-2 Termination Enable
      35. 7.7.35 CSI-2 Packet Header Control
      36. 7.7.36 Back Channel Configuration
      37. 7.7.37 Datapath Control 1
      38. 7.7.38 Remote Partner Capabilities 1
      39. 7.7.39 Partner Deserializer ID
      40. 7.7.40 Target 0 ID
      41. 7.7.41 Target 1 ID
      42. 7.7.42 Target 2 ID
      43. 7.7.43 Target 3 ID
      44. 7.7.44 Target 4 ID
      45. 7.7.45 Target 5 ID
      46. 7.7.46 Target 6 ID
      47. 7.7.47 Target 7 ID
      48. 7.7.48 Target 0 Alias
      49. 7.7.49 Target 1 Alias
      50. 7.7.50 Target 2 Alias
      51. 7.7.51 Target 3 Alias
      52. 7.7.52 Target 4 Alias
      53. 7.7.53 Target 5 Alias
      54. 7.7.54 Target 6 Alias
      55. 7.7.55 Target 7 Alias
      56. 7.7.56 Back Channel Control
      57. 7.7.57 Revision ID
      58. 7.7.58 Device Status
      59. 7.7.59 General Status
      60. 7.7.60 GPIO Pin Status
      61. 7.7.61 BIST Error Count
      62. 7.7.62 CRC Error Count 1
      63. 7.7.63 CRC Error Count 2
      64. 7.7.64 Sensor Status
      65. 7.7.65 Sensor V0
      66. 7.7.66 Sensor V1
      67. 7.7.67 Sensor T
      68. 7.7.68 CSI-2 Error Count
      69. 7.7.69 CSI-2 Error Status
      70. 7.7.70 CSI-2 Errors Data Lanes 0 and 1
      71. 7.7.71 CSI-2 Errors Data Lanes 2 and 3
      72. 7.7.72 CSI-2 Errors Clock Lane
      73. 7.7.73 CSI-2 Packet Header Data
      74. 7.7.74 Packet Header Word Count 0
      75. 7.7.75 Packet Header Word Count 1
      76. 7.7.76 CSI-2 ECC
      77. 7.7.77 IND_ACC_CTL
      78. 7.7.78 IND_ACC_ADDR
      79. 7.7.79 IND_ACC_DATA
      80. 7.7.80 FPD3_TX_ID0
      81. 7.7.81 FPD3_TX_ID1
      82. 7.7.82 FPD3_TX_ID2
      83. 7.7.83 FPD3_TX_ID3
      84. 7.7.84 FPD3_TX_ID4
      85. 7.7.85 FPD3_TX_ID5
      86. 7.7.86 Indirect Access Registers
        1. 7.7.86.1  PGEN_CTL
        2. 7.7.86.2  PGEN_CFG
        3. 7.7.86.3  PGEN_CSI_DI
        4. 7.7.86.4  PGEN_LINE_SIZE1
        5. 7.7.86.5  PGEN_LINE_SIZE0
        6. 7.7.86.6  PGEN_BAR_SIZE1
        7. 7.7.86.7  PGEN_BAR_SIZE0
        8. 7.7.86.8  PGEN_ACT_LPF1
        9. 7.7.86.9  PGEN_ACT_LPF0
        10. 7.7.86.10 PGEN_TOT_LPF1
        11. 7.7.86.11 PGEN_TOT_LPF0
        12. 7.7.86.12 PGEN_LINE_PD1
        13. 7.7.86.13 PGEN_LINE_PD0
        14. 7.7.86.14 PGEN_VBP
        15. 7.7.86.15 PGEN_VFP
        16. 7.7.86.16 PGEN_COLOR0
        17. 7.7.86.17 PGEN_COLOR1
        18. 7.7.86.18 PGEN_COLOR2
        19. 7.7.86.19 PGEN_COLOR3
        20. 7.7.86.20 PGEN_COLOR4
        21. 7.7.86.21 PGEN_COLOR5
        22. 7.7.86.22 PGEN_COLOR6
        23. 7.7.86.23 PGEN_COLOR7
        24. 7.7.86.24 PGEN_COLOR8
        25. 7.7.86.25 PGEN_COLOR9
        26. 7.7.86.26 PGEN_COLOR10
        27. 7.7.86.27 PGEN_COLOR11
        28. 7.7.86.28 PGEN_COLOR12
        29. 7.7.86.29 PGEN_COLOR13
        30. 7.7.86.30 PGEN_COLOR14
        31. 7.7.86.31 PGEN_COLOR15
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power-over-Coax
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 CSI-2 Interface
        2. 8.2.2.2 FPD-Link III Input / Output
        3. 8.2.2.3 Internal Regulator Bypassing
        4. 8.2.2.4 Loop Filter Decoupling
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Sequencing
      1. 9.1.1 System Initialization
    2. 9.2 Power Down (PDB)
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CSI-2 Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1.1 CSI-2 Guidelines

  1. Route CSI0_D*P/N pairs with controlled 100-Ω differential impedance (±20%) or 50-Ω single-ended impedance (±15%).
  2. Keep away from other high-speed signals.
  3. Keep the length difference between a differential pair to 5 mils of each other.
  4. Make sure that length matching is near the location of mismatch.
  5. Match trace lengths between the clock pair and each data pair to be < 25 mils.
  6. Separate each pair by at least 3 times the signal trace width.
  7. Keep the use of bends in differential traces to a minimum. When bends are used, the number of left and right bends must be as equal as possible, and the angle of the bend should be ≥ 135 degrees. This arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that bends have on EMI.
  8. Route all differential pairs on the same layer to help match trace impedance characteristics.
  9. Keep the number of VIAS to a minimum—TI recommends keeping the VIA count to two or fewer.
  10. Keep traces on layers adjacent to ground plane.
  11. Do NOT route differential pairs over any plane split.
Note:

Adding test points can cause impedance discontinuity and therefore negatively impacts signal performance. If test points are used, place them in series and symmetrically. Test points must not be placed in a manner that causes a stub on the differential pair.