SNLS337M October   2010  – August 2017 DS90UH926Q-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC and AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing Requirements for the Serial Control Bus
    9. 6.9  Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Input Equalization Gain
      5. 7.3.5  Common-Mode Filter Pin (CMF)
      6. 7.3.6  Video Control Signal Filter
      7. 7.3.7  EMI Reduction Features
        1. 7.3.7.1 Spread Spectrum Clock Generation (SSCG)
      8. 7.3.8  Enhanced Progressive Turnon (EPTO)
      9. 7.3.9  LVCMOS VDDIO Option
      10. 7.3.10 Power Down (PDB)
      11. 7.3.11 Stop Stream Sleep
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Oscillator Output
      14. 7.3.14 Pixel Clock Edge Select (RFB)
      15. 7.3.15 Built In Self Test (BIST)
        1. 7.3.15.1 BIST Configuration and Status
          1. 7.3.15.1.1 Sample BIST Sequence
        2. 7.3.15.2 Forward-Channel and Back-Channel Error Checking
      16. 7.3.16 Image Enhancement Features
        1. 7.3.16.1 White Balance
          1. 7.3.16.1.1 LUT Contents
          2. 7.3.16.1.2 Enabling White Balance
        2. 7.3.16.2 Adaptive HI-FRC Dithering
      17. 7.3.17 Internal Pattern Generation
      18. 7.3.18 I2S Receiving
        1. 7.3.18.1 I2S Jitter Cleaning
        2. 7.3.18.2 Secondary I2S Channel
          1. 7.3.18.2.1 MCLK
      19. 7.3.19 Interrupt Pin: Functional Description and Usage (INTB)
      20. 7.3.20 GPIO[3:0] and GPO_REG[8:4]
        1. 7.3.20.1 GPIO[3:0] Enable Sequence
        2. 7.3.20.2 GPO_REG[8:4] Enable Sequence
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State Select (OSS_SEL)
      2. 7.4.2 Low Frequency Optimization (LFMODE)
      3. 7.4.3 Configuration Select (MODE_SEL)
      4. 7.4.4 HDCP Repeater
        1. 7.4.4.1 Repeater Connections
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Display Application
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transmission Media
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DS90UH926Q-Q1, in conjunction with the DS90UH925Q-Q1, is intended for interface between a HDCP compliant host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and high definition (720p) digital video format. It allows to receive a three 8-bit RGB stream with a pixel rate up to 85 MHz together with three control bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192 kHz. The included HDCP 1.3 compliant cipher block allows the authentication of the DS90UH926Q, which decrypts both video and audio contents. The keys are pre-loaded by TI into non-volatile memory (NVM) for maximum security.

8.1.1 Display Application

The deserializer is expected to be located close to its target device. The interconnect between the deserializer and the target device is typically in the 1-inch to 3-inch separation range. The input capacitance of the target device is expected to be in the 5-pF to 10-pF range. Take care of the PCLK output trace as this signal is edge-sensitive and strobes the data. It is also assumed that the fanout of the deserializer is up to three in the repeater mode. If additional loads need to be driven, a logic buffer or mux device is recommended.

8.2 Typical Application

Figure 24 shows a typical application of the DS90UH926Q-Q1 deserializer for an 85 MHz 24-bit color display application. Inputs utilize 0.1-μF coupling capacitors to the line and the deserializer provides internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1-μF capacitors and two 4.7-μF capacitors should be used for local device bypassing. Ferrite beads are placed on the power lines for effective noise suppression. Because the device in the Pin/STRAP mode, two 10 kΩ pull-up resistors are used on the parallel output bus to select the desired device features.

The interface to the target display is with 3.3-V LVCMOS levels, thus the VDDIO pins are connected to the 3.3-V rail. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.

DS90UH926Q-Q1 30136444.gif Figure 24. Typical Connection Diagram
DS90UH926Q-Q1 30136427.gif Figure 25. Typical Display System Diagram

8.2.1 Design Requirements

For the typical design application, use the following as input parameters:

Table 12. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VDDIO 1.8 V or 3.3 V
VDD33 3.3 V
AC-Coupling Capacitor for RIN± 100 nF
PCLK Frequency 78 MHz

8.2.2 Detailed Design Procedure

8.2.2.1 Transmission Media

The DS90UH925Q-Q1 and DS90UH926Q-Q1 chipset is intended to be used in a point-to-point configuration through a shielded twisted pair cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities. The interconnect (cable and connector) between the serializer and deserializer should have a differential impedance of 100 Ω. The maximum length of cable that can be used is dependant on the quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), the electrical environment (for example, power stability, ground noise, input clock jitter, PCLK frequency, etc.) and the application environment.

The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the differential eye opening of the serial data stream. The Receiver CML Monitor Driver Output Specifications define the acceptable data eye opening width and eye opening height. A differential probe should be used to measure across the termination resistor at the CMLOUT± pin Figure 2.

8.2.3 Application Curves

DS90UH926Q-Q1 926_78m_processed.gif Figure 26. Deserializer CMLOUT Eye Diagram With 78-MHz TX Pixel Clock
DS90UH926Q-Q1 140611_091342_processed.gif Figure 27. Deserializer FPD-Link III Input With 78-MHz TX Pixel Clock