The EMB1412 MOSFET gate driver provides high peak gate drive current in 8-lead exposed-pad VSSOP package, with improved power dissipation required for high frequency operation. The compound output driver stage includes MOS and bipolar transistors operating in parallel that together sink more than 7-A peak from capacitive loads. Combining the unique characteristics of MOS and bipolar devices reduces drive current variation with voltage and temperature. Under-voltage lockout protection is provided to prevent damage to the MOSFET due to insufficient gate turn-on voltage. The EMB1412 provides both inverting and non-inverting inputs to satisfy requirements for inverting and non-inverting gate drive with a single device type.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
EMB1412 | HVSSOP (8) | 3.00 mm x 3.00 mm |
PIN | NAME | DESCRIPTION | APPLICATION INFORMATION |
---|---|---|---|
1 | IN_REF | Ground reference for control inputs | Connect to power ground (VEE) for standard positive only output voltage swing. Connect to system logic ground when VEE is connected to a negative gate drive supply. |
2 | INB | Inverting input pin | TTL compatible thresholds. Connect to IN_REF when not used. |
3 | VEE | Power ground for driver outputs | Connect to either power ground or a negative gate drive supply for positive or negative voltage swing. |
4 | IN | Non-inverting input pin | TTL compatible thresholds. Pull up to VCC when not used. |
5, 8 | N/C | Not internally connected | |
6 | VCC | Positive Supply voltage input | Locally decouple to VEE. The decoupling capacitor should be located close to the chip. |
7 | OUT | Gate drive output | Capable of sourcing 3 A and sinking 7 A. Voltage swing of this output is from VEE to VCC. |
- - - | Exposed Pad | Exposed Pad, underside of package | Internally bonded to the die substrate. Connect to VEE ground pin for low thermal impedance. |
MIN | MAX | UNIT | |
---|---|---|---|
VCC to VEE | −0.3 | 15 | V |
VCC to IN_REF | −0.3 | 15 | V |
IN/INB to IN_REF | −0.3 | 15 | V |
IN_REF to VEE | −0.3 | 5 | V |
Maximum junction temperature | 150 | °C |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature range | –55 | 150 | °C | |
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | 2 | kV |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Operating Junction Temperature | −40 | 125 | °C |
THERMAL METRIC(1) | EMB1412 | UNIT | |
---|---|---|---|
VSSOP (DGN) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 60(2) | °C/W |
RθJCbot | Junction-to-case (bottom) thermal resistance | 4.7 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY | ||||||
VCC | VCC Operating Range | VCC – IN_REF and VCC - VEE | 3.5 | 14 | V | |
UVLO | VCC Under-voltage Lockout (rising) | VCC – IN_REF | 2.4 | 3.0 | 3.5 | V |
VCCH | VCC Under-voltage Hysteresis | 230 | mV | |||
ICC | VCC Supply Current | 1.0 | 2.0 | mA | ||
CONTROL INPUTS | ||||||
VIH | Logic High | 2.3 | V | |||
VIL | Logic Low | 0.8 | V | |||
VthH | High Threshold | 1.3 | 1.75 | 2.3 | V | |
VthL | Low Threshold | 0.8 | 1.35 | 2.0 | V | |
HYS | Input Hysteresis | 400 | mV | |||
IIL | Input Current Low | IN = INB = 0 V | -1 | 0.1 | 1 | µA |
IIH | Input Current High | IN = INB = VCC | -1 | 0.1 | 1 | µA |
OUTPUT DRIVER | ||||||
ROH | Output Resistance High | IOUT = -10 mA(1) | 30 | 50 | Ω | |
ROL | Output Resistance Low | IOUT = 10 mA(1) | 1.4 | 2.5 | Ω | |
ISOURCE | Peak Source Current | OUT = VCC/2, 200 ns pulsed current | 3 | A | ||
ISINK | Peak Sink Current | OUT = VCC/2, 200 ns pulsed current | 7 | A | ||
SWITCHING CHARACTERISTICS | ||||||
td1 | Propagation Delay Time Low to High, IN/ INB rising ( IN to OUT) |
CLOAD = 2 nF | 25 | 40 | ns | |
td2 | Propagation Delay Time High to Low, IN / INB falling (IN to OUT) |
CLOAD = 2 nF | 25 | 40 | ns | |
tr | Rise time | CLOAD = 2 nF | 14 | ns | ||
tf | Fall time | CLOAD = 2 nF | 12 | ns | ||
LATCHUP PROTECTION | ||||||
AEC –Q100, METHOD 004 | TJ = 150°C | 500 | mA | |||
THERMAL RESISTANCE | ||||||
RθJA | Junction to Ambient, 0 LFPM Air Flow |
VSSOP Package | 60 | °C/W | ||
RθJC | Junction to Case | VSSOP Package | 4.7 | °C/W |
The EMB1412 is a high speed, high peak current (7 A) single channel MOSFET driver. The high peak output current of the EMB1412 will switch power MOSFETs on and off with short rise and fall times, thereby reducing switching losses considerably. The EMB1412 includes both inverting and non-inverting inputs that give the user flexibility to drive the MOSFET with either active low or active high logic signals. The driver output stage consists of a compound structure with MOS and bipolar transistor operating in parallel to optimize current capability over a wide output voltage and operating temperature range. The bipolar device provides high peak current at the critical Miller plateau region of the MOSFET VGS, while the MOS device provides rail-to-rail output swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage VCC and the power ground potential at the VEE pin.
The control inputs of the driver are high impedance CMOS buffers with TTL compatible threshold voltages. The negative supply of the input buffer is connected to the input ground pin IN_REF. An internal level shifting circuit connects the logic input buffers to the totem pole output drivers. The level shift circuit and separate input/output ground pins provide the option of single supply or split supply configurations. When driving the MOSFET gates from a single positive supply, the IN_REF and VEE pins are both connected to the power ground.
The isolated input and output stage grounds provide the capability to drive the MOSFET to a negative VGS voltage for a more robust and reliable off state. In split supply configuration, the IN_REF pin is connected to the ground of the controller which drives the EMB1412 inputs. The VEE pin is connected to a negative bias supply that can range from the IN_REF potential to as low as 14 V below the VCC gate drive supply. For reliable operation, the maximum voltage difference between VCC and IN_REF or between VCC and VEE is 14 V.
The minimum recommended operating voltage between VCC and IN_REF is 3.5 V. An Under-Voltage Lock Out (UVLO) circuit is included in the EMB1412 which senses the voltage difference between VCC and the input ground pin, IN_REF. When the VCC to IN_REF voltage difference falls below 2.8 V the driver is disabled and the output pin is held in the low state. The driver will resume normal operation when the VCC to IN_REF differential voltage exceeds 3 V.
Attention must be given to board layout when using EMB1412. Some important considerations include:
The primary goal of the thermal management is to maintain the integrated circuit (IC) junction temperature (TJ) below a specified limit to ensure reliable long term operation. The maximum TJ of IC components should be estimated in worst case operating conditions. The junction temperature can be calculated based on the power dissipated on the IC and the junction to ambient thermal resistance RθJA for the IC package in the application board and environment. The RθJA is not a given constant for the package and depends on the PCB design and the operating environment.