SLVSEB4A
February 2018 – March 2018
ESD224
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Typical Application Schematic
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings -JEDEC Specifications
6.3
ESD Ratings - IEC Specifications
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Electrical Characteristics
6.7
Typical Characteristics
7
Parameter Measurement Setup
7.1
IEC 61000-4-2 System Level ESD Test Setup with HDMI Driver for Clamping Voltage Measurement
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
IEC 61000-4-2 ESD Protection
8.3.2
IEC 61000-4-4 EFT Protection
8.3.3
IEC 61000-4-5 Surge Protection
8.3.4
IO Capacitance
8.3.5
DC Breakdown Voltage
8.3.6
Ultra Low Leakage Current
8.3.7
Low ESD Clamping Voltage
8.3.8
Supports High Speed Interfaces
8.3.9
Industrial Temperature Range
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Signal Range
9.2.2.2
Operating Frequency
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Examples
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DQA|10
MPSS004C
Thermal pad, mechanical data (Package|Pins)
DQA|10
QFND791
Orderable Information
slvseb4a_oa
6.7
Typical Characteristics
Figure 1.
Positive TLP Curve, Connector side IO Pin to GND (t
p
=100ns)
Figure 3.
Clamping voltage waveform for +8kV IEC 61000-4-2 stress. See
Figure 11
for details.
Figure 5.
IEC 61000-4-5 Surge Waveform (tp=8/20 µs)
Figure 7.
DC Voltage Sweep I-V Curve, IO Pin to GND
Figure 9.
Differential Insertion Loss
Figure 2.
Negative TLP Curve, Connector side IO Pin to GND (Plotted as positive TLP from GND to IO, t
p
=100ns )
Figure 4.
Clamping voltage waveform for -8kV IEC 61000-4-2 stress. See
Figure 11
for details.
Figure 6.
Capacitance vs. Bias Voltage at 25 degree Celsius
Figure 8.
Leakage Current vs Temperature, IO Pin to GND, at 2.5 V Bias
Figure 10.
Capacitance vs Frequency