SLVSGX0B May   2022  – November 2022 ESD752 , ESD762

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—JEDEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics – ESD752
    8. 6.8 Typical Characteristics – ESD762
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Temperature Range
      2. 7.3.2 IEC 61000-4-5 Surge Protection
      3. 7.3.3 IO Capacitance
      4. 7.3.4 Dynamic Resistance
      5. 7.3.5 DC Breakdown Voltage
      6. 7.3.6 Ultra Low Leakage Current
      7. 7.3.7 Clamping Voltage
      8. 7.3.8 Industry Standard Leaded Packages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

over TA = 25°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS DEVICE MIN TYP MAX UNIT
VRWM Reverse stand-off voltage –24 24 V
VBRF Forward breakdown voltage(1) IIO = 10 mA, IO  to GND 25.5 35.5 V
VBRR Reverse breakdown voltage(1) IIO = –10 mA, IO to GND –35.5 –25.5 V
VCLAMP Clamping voltage(3) IPP = 5.7 A, tp = 8/20 µs, IO to GND ESD752 37 V
IPP = 2.5 A, tp = 8/20 µs, from IO to GND ESD762 36 V
VCLAMP Clamping voltage(4) IPP = 16 A, TLP,  IO to GND or GND to IO ESD752 35 V
ESD762 38 V
VHold Holding voltage after snapback(5) TLP ESD752 30 V
ESD762 30 V
ILEAK Leakage current VIO = ±24 V, IO to GND -50 5 50 nA
RDYN Dynamic resistance(4) IO to GND and GND to IO ESD752 0.35 Ω
ESD762 0.57 Ω
CL Line capacitance(6) VIO = 0 V, f = 1 MHz, Vpp = 30 mV ESD752 3 5 pF
ESD762 1.7 2.8 pF
(1) Measurements made on each IO channel.
(2) VBRF and VBRR are defined as the voltage when +/- 10 mA is applied in the positive or negative direction respectively, before the device latches into the snapback state.
(3) Device stressed with 8/20 μs exponential decay waveform according to IEC 61000-4-5.
(4) Non-repetitive current pulse, Transmission Line Pulse (TLP); square pulse; ANSI / ESD STM5.5.1-2008
(5) VHOLD is defined as the lowest voltage on the TLP plot once the trigger threshold is reached and the device snapbacks and begins clamping the voltage. 
(6) Measured from IO to GND on each channel.