SPRS825F October 2012 – June 2020 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2
PRODUCTION DATA.
The Concerto family is a multicore system-on-chip microcontroller unit (MCU) with independent communication and real-time control subsystems. The F28M36x family of devices is the second series in the Concerto family.
The communications subsystem is based on the industry-standard 32-bit Arm Cortex-M3 CPU and features a wide variety of communication peripherals, including Ethernet 1588, USB OTG with PHY, Controller Area Network (CAN), UART, SSI, I2C, and an external interface.
The real-time control subsystem is based on TI’s industry-leading proprietary 32-bit C28x floating-point CPU and features the most flexible and high-precision control peripherals, including ePWMs with fault protection, and encoders and captures—all as implemented by TI’s TMS320C2000™Entry performance MCUs and Premium performance MCUs. In addition, the C28-CPU has been enhanced with the addition of the VCU instruction accelerator that implements efficient Viterbi, Complex Arithmetic, 16-bit FFTs, and CRC algorithms.
A high-speed analog subsystem and supplementary RAM memory is shared, along with on-chip voltage regulation and redundant clocking circuitry. Safety considerations also include Error Correction Code (ECC), parity, and code secure memory, as well as documentation to assist with system-level industrial safety certification.
PART NUMBER | PACKAGE | BODY SIZE |
---|---|---|
F28M36P63C2ZWT | nFBGA (289) | 16.0 mm × 16.0 mm |
F28M36P53C2ZWT | nFBGA (289) | 16.0 mm × 16.0 mm |
Changes from December 15, 2017 to June 23, 2020 (from E Revision (December 2017) to F Revision)
Table 3-1 lists the features of the F28M36x devices.
FEATURE | TYPE(1) | P63C2 | P53C2 | H53B2 | H33B2 | ||
---|---|---|---|---|---|---|---|
Master Subsystem — Arm Cortex-M3 | |||||||
Speed (MHz)(2) | – | 125 | 125 | 100 | 100 | ||
Flash (ECC) (KB) | – | 1024 | 512 | 512 | 512 | ||
RAM (ECC) (KB) | – | 16 | 16 | 16 | 16 | ||
RAM (Parity) (KB) | – | 112 | 112 | 112 | 112 | ||
IPC Message RAM (Parity) (KB) | – | 2 | 2 | 2 | 2 | ||
Security Zones | – | 2 | 2 | 2 | 2 | ||
10/100 ENET 1588 MII | 0 | Yes | Yes | No | No | ||
USB OTG FS | 0 | Yes | Yes | No | No | ||
SSI/SPI | 0 | 4 | 4 | 4 | 4 | ||
UART | 0 | 5 | 5 | 5 | 5 | ||
I2C | 0 | 2 | 2 | 2 | 2 | ||
CAN(3) | 0 | 2 | 2 | 2 | 2 | ||
µDMA | 0 | 32-ch | 32-ch | 32-ch | 32-ch | ||
EPI(4) | 0 | 1 | 1 | 1 | 1 | ||
µCRC module | 0 | 1 | 1 | 1 | 1 | ||
General-Purpose Timers | – | 4 | 4 | 4 | 4 | ||
Watchdog Timer modules | – | 2 | 2 | 2 | 2 | ||
Control Subsystem — C28x | |||||||
Speed (MHz)(2) | 150 | 150 | 150 | 150 | |||
FPU | Yes | ||||||
VCU | Yes | ||||||
Flash (ECC) (KB) | 512 | 512 | 512 | 512 | |||
RAM (ECC) (KB) | 20 | 20 | 20 | 20 | |||
RAM (Parity) (KB) | 16 | 16 | 16 | 16 | |||
IPC Message RAM (Parity) (KB) | 2 | 2 | 2 | 2 | |||
Security Zones | 1 | 1 | 1 | 1 | |||
ePWM modules | 2 | 12: 24 outputs | |||||
High-Resolution Pulse Width Modulator (HRPWM) outputs | 2 | 16 outputs | |||||
eCAP modules/PWM outputs | 0 | 6 (32-bit) | |||||
eQEP modules | 0 | 3 (32-bit) | |||||
Fault Trip Zones | – | 12 on any of 64 GPIO pins | |||||
McBSP/SPI | 1 | 1 | 1 | 1 | 1 | ||
SCI | 0 | 1 | 1 | 1 | 1 | ||
SPI | 0 | 1 | 1 | 1 | 1 | ||
I2C | 0 | 1 | 1 | 1 | 1 | ||
DMA | 0 | 6-ch | 6-ch | 6-ch | 6-ch | ||
EPI(4) | 0 | 1 | 1 | 1 | 1 | ||
32-Bit Timers | – | 3 | 3 | 3 | 3 | ||
Shared | |||||||
Shared RAM (Parity) (KB) | 64 | 64 | 64 | 0 | |||
12-Bit ADC 1 | MSPS(5) | 3 | 2.88 | 2.88 | 2.88 | 2.88 | |
Conversion Time(5) | 347 ns | 347 ns | 347 ns | 347 ns | |||
Channels | 12 | 12 | 12 | 12 | |||
Sample-and-Hold | 2 | 2 | 2 | 2 | |||
12-Bit ADC 2 | MSPS(5) | 3 | 2.88 | 2.88 | 2.88 | 2.88 | |
Conversion Time(5) | 347 ns | 347 ns | 347 ns | 347 ns | |||
Channels | 12 | 12 | 12 | 12 | |||
Sample-and-Hold | 2 | 2 | 2 | 2 | |||
Comparators with Integrated DACs | 0 | 6 | 6 | 6 | 6 | ||
Voltage Regulator | Yes – Uses 3.3-V Single Supply (3.3-V/1.2-V recommended for 125ºC) | ||||||
Clocking | See Section 6.10 | ||||||
Additional Safety | |||||||
Master Subsystem | 2 Watchdogs, NMI Watchdog: CPU, Memory | ||||||
Control Subsystem | NMI Watchdog: CPU, Memory | ||||||
Shared | Critical Register and I/O Function Lock Protection; RAM Fetch Protection | ||||||
Packaging | |||||||
Package Type | 289-Ball ZWT New Fine Pitch Ball Grid Array | Yes | Yes | Yes | Yes | ||
Junction Temperature (TJ) | T: –40°C to 105°C | – | Yes | Yes | Yes | Yes | |
S: –40°C to 125°C | – | Yes | Yes | Yes | Yes |
Cortex-M3 | 75 MHz | 125 MHz | 100 MHz |
C28x | 150 MHz | 125 MHz | 100 MHz |