SPRS825F October 2012 – June 2020 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2
PRODUCTION DATA.
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F28M36x, 72 of the possible 96 interrupts are used. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of 12 interrupt lines supports up to 8 simultaneously active interrupts. Each of the 96 interrupts has its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. Eight CPU clock cycles are needed to fetch the vector and save critical CPU registers. Hence, the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled or disabled within the PIE block.
See Table 6-16 for PIE interrupt assignments.
CPU INTERRUPTS | PIE INTERRUPTS | |||||||
---|---|---|---|---|---|---|---|---|
INTx.8 | INTx.7 | INTx.6 | INTx.5 | INTx.4 | INTx.3 | INTx.2 | INTx.1 | |
INT1 | C28.LPMWAKE
(C28LPM) 0x0D4E |
TINT0
(TIMER 0) 0x0D4C |
Reserved
– 0x0D4A |
XINT2
– 0x0D48 |
XINT1
– 0x0D46 |
Reserved
– 0x0D44 |
ADCINT2
(ADC) 0x0D42 |
ADCINT1
(ADC) 0x0D40 |
INT2 | EPWM8_TZINT
(ePWM8) 0x0D5E |
EPWM7_TZINT
(ePWM7) 0x0D5C |
EPWM6_TZINT
(ePWM6) 0x0D5A |
EPWM5_TZINT
(ePWM5) 0x0D58 |
EPWM4_TZINT
(ePWM4) 0x0D56 |
EPWM3_TZINT
(ePWM3) 0x0D54 |
EPWM2_TZINT
(ePWM2) 0x0D52 |
EPWM1_TZINT
(ePWM1) 0x0D50 |
INT3 | EPWM8_INT
(ePWM8) 0x0D6E |
EPWM7_INT
(ePWM7) 0x0D6C |
EPWM6_INT
(ePWM6) 0x0D6A |
EPWM5_INT
(ePWM5) 0x0D68 |
EPWM4_INT
(ePWM4) 0x0D66 |
EPWM3_INT
(ePWM3) 0x0D64 |
EPWM2_INT
(ePWM2) 0x0D62 |
EPWM1_INT
(ePWM1) 0x0D60 |
INT4 | EPWM9_TZINT
(ePWM9) 0x0D7E |
EPWM10_TZINT
(ePWM10) 0x0D7C |
ECAP6_INT
(eCAP6) 0x0D7A |
ECAP5_INT
(eCAP5) 0x0D78 |
ECAP4_INT
(eCAP4) 0x0D76 |
ECAP3_INT
(eCAP3) 0x0D74 |
ECAP2_INT
(eCAP2) 0x0D72 |
ECAP1_INT
(eCAP1) 0x0D70 |
INT5 | EPWM9_INT
(ePWM9) 0x0D8E |
EPWM10_INT
(ePWM10) 0x0D8C |
Reserved
– 0x0D8A |
Reserved
– 0x0D88 |
Reserved
– 0x0D86 |
EQEP3_INT
(eQEP3) 0x0D84 |
EQEP2_INT
(eQEP2) 0x0D82 |
EQEP1_INT
(eQEP1) 0x0D80 |
INT6 | EPWM11_TZINT
(ePWM11) 0x0D9E |
EPWM12_TZINT
(ePWM12) 0x0D9C |
MXINTA
(McBSPA) 0x0D9A |
MRINTA
(McBSPA) 0x0D98 |
Reserved
– 0x0D96 |
Reserved
– 0x0D94 |
SPITXINTA
(SPIA) 0x0D92 |
SPIRXINTA
(SPIA) 0x0D90 |
INT7 | EPWM11_INT
(ePWM11) 0x0DAE |
EPWM12_INT
(ePWM12) 0x0DAC |
DINTCH6
(C28 DMA) 0x0DAA |
DINTCH5
(C28 DMA) 0x0DA8 |
DINTCH4
(C28 DMA) 0x0DA6 |
DINTCH3
(C28 DMA) 0x0DA4 |
DINTCH2
(C28 DMA) 0x0DA2 |
DINTCH1
(C28 DMA) 0x0DA0 |
INT8 | Reserved
– 0x0DBE |
Reserved
– 0x0DBC |
Reserved
– 0x0DBA |
Reserved
– 0x0DB8 |
Reserved
– 0x0DB6 |
Reserved
– 0x0DB4 |
I2CINT2A
(I2CA) 0x0DB2 |
I2CINT1A
(I2CA) 0x0DB0 |
INT9 | Reserved
– 0x0DCE |
Reserved
– 0x0DCC |
Reserved
– 0x0DCA |
Reserved
– 0x0DC8 |
Reserved
– 0x0DC6 |
Reserved
– 0x0DC4 |
SCITXINTA
(SCIA) 0x0DC2 |
SCIRXINTA
(SCIA) 0x0DC0 |
INT10 | ADCINT8
(ADC) 0x0DDE |
ADCINT7
(ADC) 0x0DDC |
ADCINT6
(ADC) 0x0DDA |
ADCINT5
(ADC) 0x0DD8 |
ADCINT4
(ADC) 0x0DD6 |
ADCINT3
(ADC) 0x0DD4 |
ADCINT2
(ADC) 0x0DD2 |
ADCINT1
(ADC) 0x0DD0 |
INT11 | Reserved
– 0x0DEE |
Reserved
– 0x0DEC |
Reserved
– 0x0DEA |
Reserved
– 0x0DE8 |
MTOCIPCINT4
(IPC) 0x0DE6 |
MTOCIPCINT3
(IPC) 0x0DE4 |
MTOCIPCINT2
(IPC) 0x0DE2 |
MTOCIPCINT1
(IPC) 0x0DE0 |
INT12 | LUF
(C28FPU) 0x0DFE |
LVF
(C28FPU) 0x0DFC |
EPI_INT
(EPI) 0x0DFA |
C28RAMACCVIOL
(Memory) 0x0DF8 |
C28RAMSINGERR
(Memory) 0x0DF6 |
Reserved
– 0x0DF4 |
C28FLSINGERR
(Memory) 0x0DF2 |
XINT3
(Ext. Int. 3) 0x0DF0 |