SPRS825F October 2012 – June 2020 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2
PRODUCTION DATA.
The IPC, Shared RAMs, and Message RAMs are clocked by PLLSYSCLK. EPI is clocked by M3SSCLK. The PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK.
Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore, EPI is clocked by M3SSCLK.